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| 1/92 duty lcd controller/driver with four-level gray scale, on-chip ram the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. document no. s15745ej2v0ds00 (2nd edition) date published december 2001 ns cp(k) pD16488A data sheet 2001 mos integrated circuit the mark ? ? ? ? shows major revised points. description the pD16488A is a controller/driver which includes display ram for full-dot lcds that can provide a four-level gray scale display. this ic is able to drive full-dot lcds that contain up to 128 x 92 dots. features ? lcd controller/driver with on-chip display ram ? full dot outputs: 128 segment outputs and 92 common outputs ? can operate using single power supply (logic system) in range from 1.7 to 3.6 v. ? selection of four levels of gray scales from among 33 possible levels (four-frame rate control + 8 pulse width modulation) ? serial data input and 8-bit parallel data input (i80 series interface and m68 series interface) ? dot display ram: 128 x 128 x 2 bits ? on-chip booster: switchable from x2 to x9 modes ? selectable bias levels: 1/12 to 1/7 bias (normal display), 1/6 or 1/5 bias (partial display) ? duty settings: 1/92 to 1/1 duty ? on-chip voltage divider resistor ? on-chip oscillator ordering information part number package pD16488Ap chip pD16488Aw wafer remark purchasing the chip/wafer entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
data sheet s15745ej2v0ds 2 pD16488A table of contents 1. block diagram.............................................................................................................. ......................... 5 2. pin configuration (pad layout) ............................................................................................. ........ 6 3. pin functions.............................................................................................................. ............................ 9 3.1 power supply system pins ................................................................................................. ............................... 9 3.2 logic system pins ........................................................................................................ .................................... 10 3.3 driver-related pins...................................................................................................... ..................................... 13 3.4 test pins............................................................................................................... ............................................ 13 4. pin i/o circuits and recommended connection of unused pins...................................... 14 5. description of functions..................................................................................................... .......... 15 5.1 cpu interface ............................................................................................................... ..................................... 15 5.1.1 selection of interface type ............................................................................................... ....................... 15 5.1.2 parallel interface........................................................................................................ ............................. 15 5.1.3 serial interface.......................................................................................................... .............................. 16 5.1.4 chip select............................................................................................................... ............................... 16 5.1.5 display data ram and on-chip register access .............................................................................. ........ 16 5.2 display data ram............................................................................................................ ................................. 19 5.2.1 display data ram.......................................................................................................... ......................... 19 5.2.2 x address circuit ......................................................................................................... ............................ 19 5.2.3 column address circuit .................................................................................................... ....................... 21 5.2.4 y address circuit ......................................................................................................... ............................ 21 5.2.5 common scan circuit ....................................................................................................... ....................... 21 5.2.6 display start line set .................................................................................................... ........................... 21 5.2.7 display data latch circuit ................................................................................................ ......................... 21 5.3 blink/reverse display circuit............................................................................................... ........................... 22 5.4 oscillator.................................................................................................................. ......................................... 24 5.5 display timing generator.................................................................................................... ............................ 28 5.6 power supply circuit ........................................................................................................ ............................... 30 5.6.1 booster ................................................................................................................... ................................ 30 5.6.2 voltage regulator ......................................................................................................... ........................... 32 5.6.3 use of op amp for level power supply control .............................................................................. ........... 35 5.6.4 application examples of power supply circuits............................................................................. ........... 36 5.7 lcd display drivers ......................................................................................................... ................................ 39 5.7.1 full-dot pulse width modulation ........................................................................................... ................... 39 5.7.2 full-dot frame rate control............................................................................................... ........................ 44 data sheet s15745ej2v0ds 3 pD16488A 5.7.3 line shift driver ......................................................................................................... .............................. 45 5.7.4 display size settings ..................................................................................................... .......................... 47 5.7.5 setting of lcd ac driver's inversion cycle and ac driver's inversion position........................................ 47 5.8 display modes ............................................................................................................... ................................... 49 5.8.1 partial display mode ...................................................................................................... ......................... 49 5.8.2 monochrome (black/white) display .......................................................................................... ............... 51 5.9 reset....................................................................................................................... ........................................... 53 6. command registers.......................................................................................................... ................. 54 6.1 control register 1 (r0)................................................................................................... ................................... 55 6.2 control register 2 (r1)................................................................................................... ................................... 56 6.3 reset command (r2)........................................................................................................ ................................. 57 6.4 x address register (r3)................................................................................................... ................................. 57 6.5 y address register (r4)................................................................................................... ................................. 57 6.6 duty setting register (r5) ................................................................................................ ................................ 58 6.7 ac driver inversion cycle register (r6)................................................................................... ....................... 59 6.8 ac driver inversion position shift register (r7) .......................................................................... .................. 59 6.9 partial ac driver inversion cycle register (r8)........................................................................... ................... 60 6.10 partial ac driver inversion position shift register (r9) ................................................................. ............. 60 6.11 partial display mode setting register (r10) .............................................................................. ................... 61 6.12 display memory access register (r11)..................................................................................... .................... 61 6.13 display start line setting register (r12) ................................................................................ ...................... 62 6.14 blink x address register (r13) ........................................................................................... ........................... 62 6.15 blink start line address register (r14) .................................................................................. ...................... 62 6.16 blink end line address register (r15) .................................................................................... ..................... 62 6.17 blink data memory access register (r16).................................................................................. .................. 63 6.18 inverted x address register (r17) ........................................................................................ ......................... 63 6.19 inversion start line address register (r18) .............................................................................. ................... 63 6.20 inversion end line address register (r19) ................................................................................ .................. 64 6.21 inverted data memory (r20)............................................................................................... ............................. 64 6.22 partial start line address register (r21)................................................................................ ...................... 64 6.23 gray scale data registers 1 to 4 (r23 to r26) ............................................................................ .................. 65 6.24 partial gray scale data registers 1 to 4 (r27 to r30) .................................................................... .............. 65 6.25 power system control register 1 (r32) .................................................................................... .................... 66 6.26 power system control register 2 (r33) .................................................................................... .................... 67 6.27 power system control register 3 (r34) .................................................................................... .................... 68 6.28 electronic volume register (r35) ......................................................................................... ......................... 69 6.29 partial electronic volume register (r36) ................................................................................. ..................... 69 6.30 boost adjustment register (r37).......................................................................................... ......................... 69 6.31 ram test mode setting register (r44)..................................................................................... ..................... 70 6.32 signature read register (r45) ............................................................................................ ........................... 70 data sheet s15745ej2v0ds 4 pD16488A 7. list of pD16488A registers ........................................................................................................... 71 8. power supply sequence ...................................................................................................... ........... 72 8.1 power on sequence (when using on-chip power supply, power supply on display on) .................. 72 8.2 power off sequence (when using on-chip power supply) ...................................................................... .. 73 8.3 power on sequence (when using external driver power supply, power on display on) ................... 73 8.4 power supply off sequence (when using external driver power supply) ................................................ 74 8.5 v out , v lcd voltage sequence (power on power off) ............................................................................... 75 9. use of ram test mode ....................................................................................................... ................ 76 10. electrical specifications................................................................................................. ........... 77 11. cpu interface (reference example) ........................................................................................ 8 7 data sheet s15745ej2v0ds 5 pD16488A 1. block diagram /res /cs1 cs2 c86 psx /rd(e) /wr(r,/w) d 7 (si) d 6 (scl) d 5 to d 0 rs m/s fr fr sync dof sigin1 sigin2 tstifs tstrtst tstvihl test out osc in1 osc in2 osc out osc sync cls c9 , c9 c1a + + - v rs irs v r amp outp amp out seg 1 seg 128 com 1 com 92 v lcd v lc1 v lc2 v lc3 v lc4 v dd1 v dd2 v ss segment g/s and blink control segment driver display data latch address decoder d/a converter op amp data register i/o buffer dc/dc converter lcd voltage generator segment g/s and blink timer common driver common timing generator c1 , c1 - v out oscillator circuit timing generator command decoder register display data ram (128 x 128 x 2 bits) remark /xxx indicates active low signals. ? data sheet s15745ej2v0ds 6 pD16488A 2. pin configuration (pad layout) chip size : 3.0 x 11.4 mm 2 chip : 485 m typ. shape of alignment mark (unit: m) pad type a : pad size (ai) : 53 x 73 m 2 bump size : 45 x 60 m 2 bump height : 17 m typ. pad type b : pad size (ai) : 118 x 73 m 2 bump size : 110 x 60 m 2 bump height : 17 m typ. alignment mark coordinate mark center coordinate x [ m] y [ m] m1 ? 1200.00 5300.00 m2 ? 1200.00 ? 5300.00 m3 1275.00 ? 5475.00 m4 1275.00 5475.00 y x 403 a1 372 a4 371 1 164 a1 196 a3 197 163 100 50 50 100 50 50 100 100 50 50 100 100 a1,a2 a3 a4 ? data sheet s15745ej2v0ds 7 pD16488A ? ? ? ? pD16488A pad layout (1/2) pad pin name pad pad coordinate pad pin name pad pad coordinate pad pin name pad pad coordinate no. type x [ m] y [ m] no. type x [ m] y [ m] no. type x [ m] y [ m] 1 dummy b -1383.50 5284.00 71 vdd1 a -1383.50 690.00 141 dummy a -1383.50 -3510.00 2 dummy b -1383.50 5154.00 72 vdd1 a -1383.50 630.00 142 dummy a -1383.50 -3570.00 3 dummy b -1383.50 5024.00 73 vss a -1383.50 570.00 143 vss a -1383.50 -3630.00 4 dummy b -1383.50 4894.00 74 vss a -1383.50 510.00 144 sigin1 a -1383.50 -3690.00 5 dummy a -1383.50 4796.50 75 vss a -1383.50 450.00 145 sigin1 a -1383.50 -3750.00 6 vss a -1383.50 4590.00 76 cls a -1383.50 390.00 146 vdd1 a -1383.50 -3810.00 7 vrs a -1383.50 4530.00 77 cls a -1383.50 330.00 147 sigin2 a -1383.50 -3870.00 8 vrs a -1383.50 4470.00 78 vdd1 a -1383.50 270.00 148 sigin2 a -1383.50 -3930.00 9 ampoutp a -1383.50 4410.00 79 m/s a -1383.50 210.00 149 vss a -1383.50 -3990.00 10 ampoutp a -1383.50 4350.00 80 m/s a -1383.50 150.00 150 testout a -1383.50 -4050.00 11 ampout a -1383.50 4290.00 81 vss a -1383.50 90.00 151 testout a -1383.50 -4110.00 12 ampout a -1383.50 4230.00 82 c86 a -1383.50 30.00 152 tstifs a -1383.50 -4170.00 13 vr a -1383.50 4170.00 83 c86 a -1383.50 -30.00 153 tstifs a -1383.50 -4230.00 14 vr a -1383.50 4110.00 84 psx a -1383.50 -90.00 154 tstrtst a -1383.50 -4290.00 15 vlc4 a -1383.50 4050.00 85 psx a -1383.50 -150.00 155 tstrtst a -1383.50 -4350.00 16 vlc4 a -1383.50 3990.00 86 vdd1 a -1383.50 -210.00 156 tstvihl a -1383.50 -4410.00 17 vlc3 a -1383.50 3930.00 87 irs a -1383.50 -270.00 157 tstvihl a -1383.50 -4470.00 18 vlc3 a -1383.50 3870.00 88 irs a -1383.50 -330.00 158 vss a -1383.50 -4530.00 19 vlc2 a -1383.50 3810.00 89 vss a -1383.50 -390.00 159 dummy a -1383.50 -4796.50 20 vlc2 a -1383.50 3750.00 90 /cs1 a -1383.50 -450.00 160 dummy b -1383.50 -4894.00 21 vlc1 a -1383.50 3690.00 91 /cs1 a -1383.50 -510.00 161 dummy b -1383.50 -5024.00 22 vlc1 a -1383.50 3630.00 92 cs2 a -1383.50 -570.00 162 dummy b -1383.50 -5154.00 23 vlcd a -1383.50 3570.00 93 cs2 a -1383.50 -630.00 163 dummy b -1383.50 -5284.00 24 vlcd a -1383.50 3510.00 94 vdd1 a -1383.50 -690.00 164 dummy b -1172.50 -5474.76 25 vss a -1383.50 3450.00 95 /res a -1383.50 -750.00 165 dummy a -1075.00 -5474.76 26 vout a -1383.50 3390.00 96 /res a -1383.50 -810.00 166 com47 a -965.00 -5474.76 27 vout a -1383.50 3330.00 97 rs a -1383.50 -870.00 167 com48 a -905.00 -5474.76 28 vss a -1383.50 3270.00 98 rs a -1383.50 -930.00 168 com49 a -845.00 -5474.76 29 c9- a -1383.50 3210.00 99 vss a -1383.50 -990.00 169 com50 a -785.00 -5474.76 30 c9- a -1383.50 3150.00 100 /wr (r,/w) a -1383.50 -1050.00 170 com51 a -725.00 -5474.76 31 c9+ a -1383.50 3090.00 101 /wr (r,/w) a -1383.50 -1110.00 171 com52 a -665.00 -5474.76 32 c9+ a -1383.50 3030.00 102 /rd (e) a -1383.50 -1170.00 172 com53 a -605.00 -5474.76 33 c8- a -1383.50 2970.00 103 /rd (e) a -1383.50 -1230.00 173 com54 a -545.00 -5474.76 34 c8- a -1383.50 2910.00 104 vdd1 a -1383.50 -1290.00 174 com55 a -485.00 -5474.76 35 c8+ a -1383.50 2850.00 105 d7 a -1383.50 -1350.00 175 com56 a -425.00 -5474.76 36 c8+ a -1383.50 2790.00 106 d7 a -1383.50 -1410.00 176 com57 a -365.00 -5474.76 37 c7- a -1383.50 2730.00 107 d6 a -1383.50 -1470.00 177 com58 a -305.00 -5474.76 38 c7- a -1383.50 2670.00 108 d6 a -1383.50 -1530.00 178 com59 a -245.00 -5474.76 39 c7+ a -1383.50 2610.00 109 dummy a -1383.50 -1590.00 179 com60 a -185.00 -5474.76 40 c7+ a -1383.50 2550.00 110 d5 a -1383.50 -1650.00 180 com61 a -125.00 -5474.76 41 c6- a -1383.50 2490.00 111 d5 a -1383.50 -1710.00 181 com62 a -65.00 -5474.76 42 c6- a -1383.50 2430.00 112 d4 a -1383.50 -1770.00 182 com63 a -5.00 -5474.76 43 c6+ a -1383.50 2370.00 113 d4 a -1383.50 -1830.00 183 com64 a 55.00 -5474.76 44 c6+ a -1383.50 2310.00 114 dummy a -1383.50 -1890.00 184 com65 a 115.00 -5474.76 45 c5- a -1383.50 2250.00 115 d3 a -1383.50 -1950.00 185 com66 a 175.00 -5474.76 46 c5- a -1383.50 2190.00 116 d3 a -1383.50 -2010.00 186 com67 a 235.00 -5474.76 47 c5+ a -1383.50 2130.00 117 d2 a -1383.50 -2070.00 187 com68 a 295.00 -5474.76 48 c5+ a -1383.50 2070.00 118 d2 a -1383.50 -2130.00 188 com69 a 355.00 -5474.76 49 c4- a -1383.50 2010.00 119 dummy a -1383.50 -2190.00 189 com70 a 415.00 -5474.76 50 c4- a -1383.50 1950.00 120 d1 a -1383.50 -2250.00 190 com71 a 475.00 -5474.76 51 c4+ a -1383.50 1890.00 121 d1 a -1383.50 -2310.00 191 com72 a 535.00 -5474.76 52 c4+ a -1383.50 1830.00 122 d0 a -1383.50 -2370.00 192 com73 a 595.00 -5474.76 53 c3- a -1383.50 1770.00 123 d0 a -1383.50 -2430.00 193 dummy a 655.00 -5474.76 54 c3- a -1383.50 1710.00 124 dummy a -1383.50 -2490.00 194 dummy b 771.00 -5474.76 55 c3+ a -1383.50 1650.00 125 frsync a -1383.50 -2550.00 195 dummy b 906.00 -5474.76 56 c3+ a -1383.50 1590.00 126 frsync a -1383.50 -2610.00 196 dummy b 1041.00 -5474.76 57 c2- a -1383.50 1530.00 127 fr a -1383.50 -2670.00 197 dummy b 1274.76 -5257.50 58 c2- a -1383.50 1470.00 128 fr a -1383.50 -2730.00 198 dummy a 1274.76 -5160.00 59 c2+ a -1383.50 1410.00 129 dummy a -1383.50 -2790.00 199 dummy a 1274.76 -5100.00 60 c2+ a -1383.50 1350.00 130 dof a -1383.50 -2850.00 200 com74 a 1274.76 -5040.00 61 c1- a -1383.50 1290.00 131 dof a -1383.50 -2910.00 201 com75 a 1274.76 -4980.00 62 c1- a -1383.50 1230.00 132 oscin1 a -1383.50 -2970.00 202 com76 a 1274.76 -4920.00 63 c1+ a -1383.50 1170.00 133 oscin1 a -1383.50 -3030.00 203 com77 a 1274.76 -4860.00 64 c1+ a -1383.50 1110.00 134 oscin2 a -1383.50 -3090.00 204 com78 a 1274.76 -4800.00 65 c1a a -1383.50 1050.00 135 oscin2 a -1383.50 -3150.00 205 com79 a 1274.76 -4740.00 66 c1a a -1383.50 990.00 136 oscout a -1383.50 -3210.00 206 com80 a 1274.76 -4680.00 67 vdd2 a -1383.50 930.00 137 oscout a -1383.50 -3270.00 207 com81 a 1274.76 -4620.00 68 vdd2 a -1383.50 870.00 138 dummy a -1383.50 -3330.00 208 com82 a 1274.76 -4560.00 69 vdd2 a -1383.50 810.00 139 oscsync a -1383.50 -3390.00 209 com83 a 1274.76 -4500.00 70 vdd1 a -1383.50 750.00 140 oscsync a -1383.50 -3450.00 210 com84 a 1274.76 -4440.00 data sheet s15745ej2v0ds 8 pD16488A ? ? ? ? pD16488A pad layout (2/2) pad pin name pad pad coordinate pad pin name pad pad coordinate pad pin name pad pad coordinate no. type x [ m] y [ m] no. type x [ m] y [ m] no. type x [ m] y [ m] 211 com85 a 1274.76 -4380.00 281 seg67 a 1274.76 -180.00 351 com45 a 1274.76 4020.00 212 com86 a 1274.76 -4320.00 282 seg66 a 1274.76 -120.00 352 com44 a 1274.76 4080.00 213 com87 a 1274.76 -4260.00 283 seg65 a 1274.76 -60.00 353 com43 a 1274.76 4140.00 214 com88 a 1274.76 -4200.00 284 seg64 a 1274.76 0.00 354 com42 a 1274.76 4200.00 215 com89 a 1274.76 -4140.00 285 seg63 a 1274.76 60.00 355 com41 a 1274.76 4260.00 216 com90 a 1274.76 -4080.00 286 seg62 a 1274.76 120.00 356 com40 a 1274.76 4320.00 217 com91 a 1274.76 -4020.00 287 seg61 a 1274.76 180.00 357 com39 a 1274.76 4380.00 218 com92 a 1274.76 -3960.00 288 seg60 a 1274.76 240.00 358 com38 a 1274.76 4440.00 219 dummy a 1274.76 -3900.00 289 seg59 a 1274.76 300.00 359 com37 a 1274.76 4500.00 220 seg128 a 1274.76 -3840.00 290 seg58 a 1274.76 360.00 360 com36 a 1274.76 4560.00 221 seg127 a 1274.76 -3780.00 291 seg57 a 1274.76 420.00 361 com35 a 1274.76 4620.00 222 seg126 a 1274.76 -3720.00 292 seg56 a 1274.76 480.00 362 com34 a 1274.76 4680.00 223 seg125 a 1274.76 -3660.00 293 seg55 a 1274.76 540.00 363 com33 a 1274.76 4740.00 224 seg124 a 1274.76 -3600.00 294 seg54 a 1274.76 600.00 364 com32 a 1274.76 4800.00 225 seg123 a 1274.76 -3540.00 295 seg53 a 1274.76 660.00 365 com31 a 1274.76 4860.00 226 seg122 a 1274.76 -3480.00 296 seg52 a 1274.76 720.00 366 com30 a 1274.76 4920.00 227 seg121 a 1274.76 -3420.00 297 seg51 a 1274.76 780.00 367 com29 a 1274.76 4980.00 228 seg120 a 1274.76 -3360.00 298 seg50 a 1274.76 840.00 368 com28 a 1274.76 5040.00 229 seg119 a 1274.76 -3300.00 299 seg49 a 1274.76 900.00 369 dummy a 1274.76 5100.00 230 seg118 a 1274.76 -3240.00 300 seg48 a 1274.76 960.00 370 dummy a 1274.76 5160.00 231 seg117 a 1274.76 -3180.00 301 seg47 a 1274.76 1020.00 371 dummy b 1274.76 5257.50 232 seg116 a 1274.76 -3120.00 302 seg46 a 1274.76 1080.00 372 dummy b 1041.00 5474.76 233 seg115 a 1274.76 -3060.00 303 seg45 a 1274.76 1140.00 373 dummy b 906.00 5474.76 234 seg114 a 1274.76 -3000.00 304 seg44 a 1274.76 1200.00 374 dummy b 771.00 5474.76 235 seg113 a 1274.76 -2940.00 305 seg43 a 1274.76 1260.00 375 com27 a 595.00 5474.76 236 seg112 a 1274.76 -2880.00 306 seg42 a 1274.76 1320.00 376 com26 a 535.00 5474.76 237 seg111 a 1274.76 -2820.00 307 seg41 a 1274.76 1380.00 377 com25 a 475.00 5474.76 238 seg110 a 1274.76 -2760.00 308 seg40 a 1274.76 1440.00 378 com24 a 415.00 5474.76 239 seg109 a 1274.76 -2700.00 309 seg39 a 1274.76 1500.00 379 com23 a 355.00 5474.76 240 seg108 a 1274.76 -2640.00 310 seg38 a 1274.76 1560.00 380 com22 a 295.00 5474.76 241 seg107 a 1274.76 -2580.00 311 seg37 a 1274.76 1620.00 381 com21 a 235.00 5474.76 242 seg106 a 1274.76 -2520.00 312 seg36 a 1274.76 1680.00 382 com20 a 175.00 5474.76 243 seg105 a 1274.76 -2460.00 313 seg35 a 1274.76 1740.00 383 com19 a 115.00 5474.76 244 seg104 a 1274.76 -2400.00 314 seg34 a 1274.76 1800.00 384 com18 a 55.00 5474.76 245 seg103 a 1274.76 -2340.00 315 seg33 a 1274.76 1860.00 385 com17 a -5.00 5474.76 246 seg102 a 1274.76 -2280.00 316 seg32 a 1274.76 1920.00 386 com16 a -65.00 5474.76 247 seg101 a 1274.76 -2220.00 317 seg31 a 1274.76 1980.00 387 com15 a -125.00 5474.76 248 seg100 a 1274.76 -2160.00 318 seg30 a 1274.76 2040.00 388 com14 a -185.00 5474.76 249 seg99 a 1274.76 -2100.00 319 seg29 a 1274.76 2100.00 389 com13 a -245.00 5474.76 250 seg98 a 1274.76 -2040.00 320 seg28 a 1274.76 2160.00 390 com12 a -305.00 5474.76 251 seg97 a 1274.76 -1980.00 321 seg27 a 1274.76 2220.00 391 com11 a -365.00 5474.76 252 seg96 a 1274.76 -1920.00 322 seg26 a 1274.76 2280.00 392 com10 a -425.00 5474.76 253 seg95 a 1274.76 -1860.00 323 seg25 a 1274.76 2340.00 393 com9 a -485.00 5474.76 254 seg94 a 1274.76 -1800.00 324 seg24 a 1274.76 2400.00 394 com8 a -545.00 5474.76 255 seg93 a 1274.76 -1740.00 325 seg23 a 1274.76 2460.00 395 com7 a -605.00 5474.76 256 seg92 a 1274.76 -1680.00 326 seg22 a 1274.76 2520.00 396 com6 a -665.00 5474.76 257 seg91 a 1274.76 -1620.00 327 seg21 a 1274.76 2580.00 397 com5 a -725.00 5474.76 258 seg90 a 1274.76 -1560.00 328 seg20 a 1274.76 2640.00 398 com4 a -785.00 5474.76 259 seg89 a 1274.76 -1500.00 329 seg19 a 1274.76 2700.00 399 com3 a -845.00 5474.76 260 seg88 a 1274.76 -1440.00 330 seg18 a 1274.76 2760.00 400 com2 a -905.00 5474.76 261 seg87 a 1274.76 -1380.00 331 seg17 a 1274.76 2820.00 401 com1 a -965.00 5474.76 262 seg86 a 1274.76 -1320.00 332 seg16 a 1274.76 2880.00 402 dummy a -1075.00 5474.76 263 seg85 a 1274.76 -1260.00 333 seg15 a 1274.76 2940.00 403 dummy b -1172.50 5474.76 264 seg84 a 1274.76 -1200.00 334 seg14 a 1274.76 3000.00 265 seg83 a 1274.76 -1140.00 335 seg13 a 1274.76 3060.00 266 seg82 a 1274.76 -1080.00 336 seg12 a 1274.76 3120.00 267 seg81 a 1274.76 -1020.00 337 seg11 a 1274.76 3180.00 268 seg80 a 1274.76 -960.00 338 seg10 a 1274.76 3240.00 269 seg79 a 1274.76 -900.00 339 seg9 a 1274.76 3300.00 270 seg78 a 1274.76 -840.00 340 seg8 a 1274.76 3360.00 271 seg77 a 1274.76 -780.00 341 seg7 a 1274.76 3420.00 272 seg76 a 1274.76 -720.00 342 seg6 a 1274.76 3480.00 273 seg75 a 1274.76 -660.00 343 seg5 a 1274.76 3540.00 274 seg74 a 1274.76 -600.00 344 seg4 a 1274.76 3600.00 275 seg73 a 1274.76 -540.00 345 seg3 a 1274.76 3660.00 276 seg72 a 1274.76 -480.00 346 seg2 a 1274.76 3720.00 277 seg71 a 1274.76 -420.00 347 seg1 a 1274.76 3780.00 278 seg70 a 1274.76 -360.00 348 dummy a 1274.76 3840.00 279 seg69 a 1274.76 -300.00 349 dummy a 1274.76 3900.00 280 seg68 a 1274.76 -240.00 350 com46 a 1274.76 3960.00 data sheet s15745ej2v0ds 9 pD16488A 3. pin functions 3.1 power supply system pins symbol name pad no. i/o description v dd1 logic power supply pin 70-72, 78, 86, 94, 104, 146 ? power supply pin for logic circuit v dd2 boost circuit power supply pin 67-69 ? power supply pin for booster v ss logic and driver ground pin 6, 25, 28, 73 to 75, 81, 89, 99, 143, 149, 158 ? ground pin for logic and driver circuits v out driver power supply pin 26, 27 ? power supply pin for driver. output pin for on-chip booster. connect a 1 f boost capacitor between this pin and the gnd pin. if not using the on-chip booster, a direct driver power supply can be input. v lcd , v lc1 to v lc4 reference power supply pins for driver 24, 23, 22 to 15 ? these are reference power supply pins for the lcd driver. connect a capacitor between these pins and the gnd pin if an internal bias has been selected. c1 + , c1 ? c2 + , c2 ? c3 + , c3 ? c4 + , c4 ? c5 + , c5 ? c6 + , c6 ? c7 + , c7 ? c8 + , c8 ? c9 + , c9 ? boost capacitor connection pins (1) 64, 63, 62, 61 60, 59, 58, 57 56, 55, 54, 53 52, 51, 50, 49 48, 47, 46, 45 44, 43, 42, 41 40, 39, 38, 37 36, 35, 34, 33 32, 31, 30, 29 ? these are capacitor connection pins for the booster. when using the on-chip booster, connect a 1 f capacitor between positive (+) and negative (-) pins. c1a boost capacitor connection pin (2) 65, 66 ? this is a capacitor connection pin for boost adjustment. when using the on-chip booster, connect a 1 f capacitor between this pin and the gnd pin. data sheet s15745ej2v0ds 10 pD16488A 3.2 logic system pins (1/3) symbol name pad no. i/o description psx data transfer selection 84, 85 input this pin is used to select between parallel data input and serial data input. psx = h: parallel data input psx = l: serial data input /cs1, cs2 chip select 90, 91, 92, 93 input these pins are used for chip select signals. when /cs1 = l (cs2 = h), the chip is active and can perform data input/output operations including command and data i/o. /rd (e) read (enable) 102, 103 input when i80 series parallel data transfer (/rd) has been selected, the signal at this pin is used to enable read operations. data is output to the data bus only when this pin is l. when m68 series parallel data transfer (e) has been selected, the signal at this pin is used to enable write operations. data is written at the falling edge of this signal. /wr (r,/w) write (read/write) 100, 101 input when i80 series parallel data transfer (/wr) has been selected, the signal at this pin is used to enable write operations. data is written at the rising edge of this signal. when 68 series parallel data transfer (r,/w) has been selected, this pin is used to determine the direction of data transfer. l: write h: read c86 interface selection 82, 83 input this pin is used to switch between interface modes (i80 series cpu or m68 series cpu). l: selects i80 series cpu mode h: selects m68 series cpu mode d 0 to d 5 , d 6 (scl) d 7 (si) data bus (serial clock) (serial input) 105 to 108, 110 to 113, 115 to 118, 120 to 123 i/o these pins comprise an 8-bit bidirectional data bus that connects to an 8-bit or 16-bit standard cpu bus. when the serial interface has been selected (psx = l), d 6 functions as a serial clock input pin (scl) and d 7 functions as a serial data input pin (si). in either case, pins d 0 to d 5 are in high impedance mode. when the chip is not selected, d 0 to d 7 are in high impedance mode. rs index register/data, command selection 97, 98 input usually, this pin is connected to the lsb of the standard cpu address bus and is used to distinguish between data from index registers and data/commands. rs = h : indicates that data from d 0 to d 7 is data/command rs = l : indicates that data from d 0 to d 7 is index register contents /res reset 95, 96 input when /res is low, an internal reset is performed. the reset operation is executed at the /res signal level. data sheet s15745ej2v0ds 11 pD16488A (2/3) symbol name pad no. i/o description cls select clock division 76, 77 input this pin is used to select whether or not to use the divider within the display clock oscillator. cls = h: use divider cls = l: do not use divider when using an external clock, the cls = l setting is input via the osc in1 and osc in2 pins as normal and partial clocks respectively. when cls = h, clock input is via the os cin1 pin only. fr frame signal 127, 128 i/o this pin is used as i/o pin for the lcd's ac conversion signal. m/s = h: output m/s = l: input when using the pD16488A in master/slave mode, both fr pins must be connected. fr sync frame synchronization signal 125, 126 i/o this pin is used as i/o pin for the lcd's ac conversion synchronization signal. m/s = h: output m/s = l: input when the pD16488A is used in master/slave mode, both fr sync pins must be connected. dof display blink 130, 131 i/o this pin is used to control the lcd's display blink function. m/s = h: output m/s = l: input when the pD16488A is used in master/slave mode, both dof pins must be connected. this pin is used to select between master and slave operation modes. in master operation mode, it outputs the timing signal required by the lcd driver and in slave operation mode it inputs this timing signal from an external source for use in lcd display synchronization. m/s = h: master operation mode m/s = l: slave operation mode settings dependent on the m/s mode are listed in the following chart. m/s power supply circuit fr fr sync dof h valid output output output l invalid input input input m/s master/slave 79, 80 input irs v lcd regulation 87, 88 input this pin is used to select the resistor that is used for v lcd voltage regulation. irs = h: uses internal resistor irs = l: does not use internal resistor. the v lcd voltage level is regulated using the external voltage division resistor that is connected to the v r pin. this pin is valid only in master operation mode. in slave operation mode, this pin is fixed high or low level. sigin1, sigin2 signature setting pins 144, 145, 147, 148 input these pins can be used to set a unique signature for the ic. the signal set via these pins can subsequently be read from the signature read register (r45). ? data sheet s15745ej2v0ds 12 pD16488A (3/3) symbol name pad no. i/o description osc in1 132, 133 input osc in2 134, 135 input osc out oscillation signal pins 136, 137 output a resistor can be inserted between osc in1 -osc out , and osc in2 -osc out . when using an external oscillator, a clock signal is input via the osc in pins according to the cls pin's status and the osc out pin is left unconnected. the wiring between osc in1 -osc out and osc in2 -osc out must be as short as possible, and use after proper evaluation. osc sync display clock output 139, 140 output display clock output pin. see 5. 4 oscillator concerning use or this pin when the pD16488A is in master or slave operation mode. data sheet s15745ej2v0ds 13 pD16488A 3.3 driver-related pins symbol name pad no. i/o description seg 1 to seg 128 segment 347-220 output segment output pins com 1 to com 92 common 166 to 192, 200 to 218, 350 to 368, 375 to 401 output common output pins v rs op amp input pin for regulating the driving voltage of the lcd 7, 8 input v rs is an op amp input pin for regulating the driving voltage of the lcd. this is a reference voltage input for the lcd voltage regulation amplifier. when using the internal drive circuit (i.e., when op1 = 1), we recommend inserting a 0.1 to 1 f capacitor between this pin and gnd. v r input pin for the op amp's feedback connection 13, 14 input v r is an input for the op amp's feedback connection. insert this pin between gnd and amp out when using the feedback resistor for this input. this pin is valid only when not using an internal resistor for v lcd voltage regulation (i.e., when irs = l). this pin cannot be used when using the internal resistor for v lcd voltage regulation (i.e., when irs = h). amp out 9, 10 amp outp op amp output 11, 12 output these are op amp output pins for regulating the driving voltage of the lcd. when not using an internal resistor for v lcd voltage regulation (i.e., when irs = l), these outputs are connected to the lcd drive voltage regulation resistor (see 5.6.2 voltage regulator ). we recommend inserting a 0.01 to 0.1 f capacitor between these pins in order to stabilize the internal op amp's output. dummy dummy pin 1 to 5, 109, 114, 119, 124, 129, 138, 141, 142, 159 to 165, 193 to 199, 219, 348, 349, 369 to 374, 402, 403 ? dummy pin. these pins are not connected inside ic. usually, leave these pins open. 3.4 test pins symbol name pad no. i/o description tstifs tstrtst tstvihl test input 152, 153, 154, 155, 156, 157 input these pins are used to set a test mode for the ic. normally, connect these pins to v ss . test out test output 150, 151 output these pins are used when the ic is in test mode. usually, leave them open. data sheet s15745ej2v0ds 14 pD16488A 4. pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are described below. pin name input type input/output recommended connection of unused pins notes psx schmitt trigger input mode setting pin. note 1 /cs1 filter input connect to v ss . ? ? ? ? cs2 filter input connect to v dd1 . ? ? ? ? /rd(e) filter input connect to v dd1 (i80 series interface), connect to v dd1 or v ss (serial interface). ? ? ? ? /wr(r,/w) filter input connect to v dd1 or v ss (serial interface). ? ? ? ? c86 schmitt trigger input mode setting pin. note 1 d 0 to d 5 filter input/output leave open ? ? ? ? d 6 (scl) filter input/output ? ? ? ?? ? ? ? d 7 (si) filter input/output ? ? ? ?? ? ? ? rs filter input register setting pin. note 2 /res schmitt trigger input connect to v dd1 . ? ? ? ? cls schmitt trigger input mode setting pin note 1 fr cmos input/output leave open (using master mode, m/s = h). ? ? ? ? fr sync cmos input/output leave open (using master mode, m/s = h). ? ? ? ? dof cmos input/output leave open (using master mode, m/s = h). ? ? ? ? m/s schmitt trigger input mode setting pin. note 1 irs schmitt trigger input mode setting pin. note 1 sigin1 schmitt trigger input connect to v dd1 or v ss . ? ? ? ? sigin2 schmitt trigger input connect to v dd1 or v ss . ? ? ? ? osc in1 schmitt trigger input ? ? ? ?? ? ? ? osc in2 schmitt trigger input connect to v dd1 or v ss (cls = h) ? ? ? ? osc out ? ? ? ? output leave open (when using external clock) ? ? ? ? osc sync ? ? ? ? output leave open ? ? ? ? tstifs schmitt trigger input connect to v ss (during normal use) ? ? ? ? tstrtst schmitt trigger input connect to v ss (during normal use) ? ? ? ? tstvihl schmitt trigger input connect to v ss (during normal use) ? ? ? ? test out output leave open notes 1. connect to either v dd1 or v ss , depending on the mode setting. 2. input either v dd1 or v ss output from cpu, depending on the mode setting. data sheet s15745ej2v0ds 15 pD16488A 5. description of functions 5.1 cpu interface 5.1.1 selection of interface type the pD16488A chip transfers data using an 8-bit bidirectional data bus (d 7 to d 0 ) or a serial data input (si). setting the polarity of the psx pin as either h (high) or l (low) selects between 8-bit parallel or serial data input, as shown in the following table. psx cs rs /rd /wr c86 d 7 d 6 d 5 to d0 h: parallel input cs rs /rd /wr c86 d 7 d 6 d 5 to d0 l: serial input cs rs note1 note1 note1 si scl hi-z note2 notes 1. fixed as either high or low. 2. hi-z: high impedance 5.1.2 parallel interface when the parallel interface has been selected (psx = h), setting the c86 pin as either h or l enables a direct connection to an i80 series or m68 series cpu (see table below). c86 /cs1 cs2 rs /rd /wr d 7 to d 0 h: m68 series cpu /cs1 cs2 rs e r,/w d 7 to d 0 l: i80 series cpu /cs1 cs2 rs /rd /wr d 7 to d 0 the data bus signal is identified according to the combination of the rs, /rd(e), and /wr(r,/w) signals, as shown in the following table. common m68 i80 function rs r,/w /rd /wr 1 1 0 1 reads display data and registers 1 0 1 0 writes display data and registers 0 1 0 1 prohibited 0 0 1 0 writes to index register ? data sheet s15745ej2v0ds 16 pD16488A 5.1.3 serial interface when the serial interface has been selected (psx = l), if the chip is active (/cs1 = l, cs2 = h), serial data input (si) and serial clock input (scl) can be received. serial data is read from d 7 and then from d 6 to d 0 on the rising edge of the serial clock, via the serial input pin. this data is synchronized on the eighth serial clock's rising edge and is then converted to parallel data for processing. rs input is used to judge serial input data as display data or command data: when rs = h the data is display/command data and when rs = l the data is index data. when the chip enters active mode, rs input is read at the rising edge after every eighth serial clock and is then used to judge the serial input data. the serial interface signa l chart is shown below. figure 5-1. serial interface signal chart d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 123456789101112131415161718 /cs1 si scl rs cs2 = h remarks 1. if the chip is not active, the shift register and counter are reset to their initial settings. 2. the data read function is disabled during serial interface mode. 3. when using scl wiring, take care concerning the possible effects of terminating reflection and noise from external sources. we recommend checking operation with the actual device. 5.1.4 chip select the pD16488A has two chip select pins (/cs1 and cs2). the cpu parallel interface or serial interface can be used only when /cs1 = l and cs2 = h. when chip select is inactive, p 0 to p 7 are set to high impedance (invalid) and input of rs, /rd, or /wr is not active. if serial interface mode has been set, the shift register and counter are both reset. 5.1.5 display data ram and on-chip register access because only the required cycle time (t cyc ) is satisfied when accessing the pD16488A from the cpu, high-speed data transfer is possible. there is no need to consider any wait time. no dummy data is needed when writing data. even when data is read, there is no need for dummy data except in the display memory access register (r11). in other words, dummy data is required only when reading data from the display memory access register (r11). figure 5-2 illustrates this relationship. data sheet s15745ej2v0ds 17 pD16488A figure 5-2. write and read (1/2) write data sheet s15745ej2v0ds 18 pD16488A figure 5-2. write and read (2/2) read (other than display memory access register) data sheet s15745ej2v0ds 19 pD16488A 5.2 display data ram 5.2.1 display data ram this is the ram that is used to store the display's dot data. the ram configuration is 256 bits (32 x 8 bits) x 128 bits. a ny specified bit can be accessed by selecting the corresponding x address and y address. d 0 to d 7 are the display data sent from the cpu, and correspond to segx on the lcd display (see figure 5-3). the cpu writes data to and reads data from the display ram via the i/o buffer, and these read/write operations are independent of the signal read operations for the lcd driver. accordingly, there are no adverse effects (such as flicker) in the lcd display when display data ram is accessed asynchronously. figure 5-3. display data ram 0111 00 1000 00 0000 00 0111 00 1000 00 com 0 seg 1 d 7 d 6 d 5 d 4 seg 2 com 1 com 2 com 3 com 4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 msb pixel 1 pixel 2 pixel 3 pixel 4 lsb pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 x address 00h x address 01h pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 pixel 1 pixel 2 pixel 3 pixel 4 display data lcd display lcd panel 5.2.2 x address circuit as shown in figure 5-4, the display data ram's x address is specified via the x address register (r3). when using x address increment mode (inc = 0: control register 2 (r1)), the specified x address is incremented (by 1) each time a display data read or write operation is executed. the cpu is able to continuously access the display data. the x address is incremented to 1fh, after which the y address is incremented after each read or write operation and the x address is set back to 00h. for monochrome (black-and-white) display, the x address is incremented to 0fh, after which the y address is incremented after each read or write operation and the x address is set back to 00h. data sheet s15745ej2v0ds 20 pD16488A figure 5-4. configuration of x address register com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com30 com31 d4 data x address d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h com33 21h com34 22h com35 23h com36 24h com37 25h com38 76h com83 77h com84 78h com85 79h com86 7ah com87 7bh com88 7ch com89 7dh com90 7eh com91 7fh com92 0 d0 1 d0 seg1 seg2 seg3 seg4 seg5 seg6 01h 02h 7dh 03h 01h 1fh 1 1 1 1 seg128 seg125 seg126 seg127 7fh 00h 7eh 7dh seg7 seg8 7ch 04h 07h 7bh 05h 7ah 06h 79h 78h 7fh 00h 0 0 0 0 adc 7ch 03h 7eh 01h 02h 00h 0 0 0 0 0 1 1 com output yaddress start column address lcd output com27 com28 com29 com32 com9 com10 com11 com12 com13 com14 com3 com4 com5 com6 com7 com8 com1 com2 92-line data sheet s15745ej2v0ds 21 pD16488A 5.2.3 column address circuit when displaying the contents of the display data ram, the column address corresponds to the seg output, as shown in figure 5-4. as is shown in table 5-1, the correspondence between the display ram's column address and segment output can be inverted using the adc flag in control register 1 (r0) (segment driver direction selection flag). this reduces the constraints on chip layout when assembling the lcd module. table 5-1. relationship between column address and seg output seg output seg 1 seg 128 0 00h column address 7fh adc (d 1 ) 17fh column address 00h 5.2.4 y address circuit as is shown in figure 5-4, the y address register (r4) is used to specify the display data ram's y address. when using y address increment mode (inc = 1: control register 2 (r1)), the specified y address is incremented (by 1) each time a display data read or write operation is executed. the cpu is able to continuously access the display data. the y address is incremented to 7fh, after which the x address is incremented after each read or write operation and the y address is set back to 00h. 5.2.5 common scan circuit the common scan circuit sets the scan lines for common signals. the scan direction is set using the comr flag in control register 1 (r0), as shown in table 5-2. for example, when using 1/80 duty, when comr = l the scan direction is com 1 com 80 and when comr = h, the scan direction is com 80 com 1 using the com 80 to com 1 pins. table 5-2. relationship between common scan circuit and scan direction 0com 1 com 92 comr (d 0 ) 1com 92 com 1 5.2.6 display start line set as is shown in figure 5-4, display start line set specifies the y address that corresponds to the com 1 output for displaying the contents of display data ram. the display start line setting register (r12) is used to specify the top line in the display . the screen can be scrolled, overwritten, etc. a 7-bit display start address is set to the display start line setting register. 5.2.7 display data latch circuit the display data latch circuit is used for temporary storage of data that is output to the lcd driver from the display data r am. the display scan command that sets normal or reverse display mode and the display on/off command control latched data so that there is no effect on the data in the display data ram. ? data sheet s15745ej2v0ds 22 pD16488A 5.3 blink/reverse display circuit the pD16488A enables blinking display and reverse display in designated parts of the full dot display. a blinking display is achieved by cycling on/off (level 0 when four-level gray scale mode has been selected) at approximately 1 hz and reverse display is achieved by inverting the display level value. the area designated for blinking is specified via the blink start/end line address registers (r14 and r15), the blink x address register (r13), and the blink data memory access register (r16). first, the blinking display's start and end line addresses are selected via the blink start/end line address registers. next , the blink x address register (r13) and the blink data memory (r16) are used to select the column for the blinking display. the inversion start/end line address registers (r18 and r19), the inverted x address register (r17), and the inverted data memory access register (r20) are used to select the reverse display area. first, the inversion start/end line address registers (r18 and r19) are set to select the line addresses where the reverse display will start and end. next, the inverted x address register (r17) and the inverted data memory access register (r20) are used to select the column for the reverse display. the specified blink/inverted x address is incremented (by 1) with each input of blink/reverse display data. the blink ram and inversion ram, which have a 128 bit (16 x 8 bit) configuration, are used to store data for blinking display and reverse display respectively. to access the desired bit, simply specify the corresponding x address. the blink/reverse data (data bits d 0 to d 7 sent from the cpu) correspond to segx on the lcd display, as shown in figure 5-5. after the area and data settings are complete, the bld bit and ivd bit in the control register 1 (r0) are set to h, at which point the blinking and/or reverse display of data begins. figure 5-6 illustrates the relationship between the start line addres s, end line address, blink/reverse data, and lcd display. table 5-3. inversion manipulation and display original level after inversion four-level gray scale display mode 0, 0 1, 1 0, 1 1, 0 1, 0 0, 1 1, 1 0, 0 b/w display mode 10 01 figure 5-5. correspondence between blink/reverse data and segments d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 78h 79h 7ah 7bh 7ch 7dh 7eh 7fh 0 d0 7eh 7fh 7dh 7ch 7bh 7ah 79h 78h 77h 76h 75h 74h 73h 72h 71h 70h 07h 08h 05h 04h 03h 02h 01h 00h 1 d0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg121 seg122 seg123 seg124 seg125 seg126 seg127 seg128 1 1 1 0 0 0 adc column address lcd output 1 1 0 0 0 0 00h data 01h 0fh x address data sheet s15745ej2v0ds 23 pD16488A figure 5-6. setting image of blink/reverse display area n n+1 n+2 n+3 n+4 n+5 n+6 n+7 001 1 0 00 1 0001 1 00 0 0010 1 00 1 0010 1 00 1 0001 1 00 0 0011 0 00 1 0011 0 00 1 0001 1 00 0 yes no blink/revese data blinking or reverse display pixels. blink/inversion start line address register blink/inversion end line address register blink/inverted x address register control register 1 (bld, ivd = h) blink/inverted data memory access register data write completed ? example of sequence for setting blink/reverse display end line start line start end data sheet s15745ej2v0ds 24 pD16488A 5.4 oscillator the pD16488A include a cr-type oscillator (r external) for normal and partial display, which generates the display clocks. the clocks from this oscillator are controlled via the cls pin and the dty flag in the control register 2 (r1). the clock configuration for the display can be set to suit the target system. the functions of this circuit are described below. ? the oscillator for normal and partial display is enabled only when resistors rn and rp have been connected. the dty flag in the control register 2 (r1) and the cls pin status are used to switch between the oscillation clocks for normal display and partial display modes. ? the divider divides the external clock that has been input for the normal oscillator and the normal display into a clock for partial display. the external clock that is input for the partial oscillator and partial display is also divided for the partial display. ? the division level is automatically set for the divider based on the relationship between the on/off status of the divider setting pin (cls pin) and the duty of the specified partial display, as shown in table 5-4. figure 5-7. oscillator block osc in1 osc in2 osc out tosc sync cls mux normal display/ partial display oscillator partial display divider normal/partial signal selected via dty/cls signal to select division level for partial display to graphic driver the relationship between the frame frequency (f frame ), oscillation frequency (f oscin1 ), and setting duty (in normal display mode) is described below. f frame = f oscin1 8 n (in four-level gray scale display mode) f frame = f oscin1 4 n (in b/w display mode) n = 1/n duty (setting duty) data sheet s15745ej2v0ds 25 pD16488A table 5-4. setting of division level for partial display and static icon display in four-level gray scale display mode (gray = l, control register 2 (r1)) display mode normal display duty ratio partial display duty ratio division source osc in1 /osc in2 divider on/off cls normal/partial select dty partial division ratio comments 1/38 1/25 l(off) 1/12 1/38 1/25 h(on) 1/12 osc in1 l (normal) ? 1/38 1/1 partial frame frequency: f oscin2 /8 /38 1/25 osc in2 l(off) 1/1 partial frame frequency: f oscin2 /8 /25 1/12 1/2 partial frame frequency: f oscin2 /2(division ratio) /8 /12 1/38 1/2 partial frame frequency: f oscin1 /2(division ratio) /8 /38 1/25 osc in1 h(on) 1/2 partial frame frequency: f oscin1 /2(division ratio) /8 /25 1/1 to 1/80 1/12 h (partial) 1/4 partial frame frequency: f oscin1 /4(division ratio) /8 /12 1/38 1/25 l(off) 1/12 1/38 1/25 h(on) 1/12 osc in1 l (normal) ? 1/38 1/1 partial frame frequency: f oscin2 /8 /38 1/25 osc in2 l(off) 1/1 partial frame frequency: f oscin2 /8 /25 1/12 1/2 partial frame frequency: f oscin2 /2(division ratio) /8 /12 1/38 1/2 partial frame frequency: f oscin1 /2(division ratio) /8 /38 1/25 osc in1 h(on) 1/4 partial frame frequency: f oscin1 /4(division ratio) /8 /25 four-level gray scale gray = l 1/81 to 1/92 1/12 h (partial) 1/8 partial frame frequency: f oscin1 /8(division ratio) /8 /12 in black/white display mode (gray = h, control register 2 (r1)) display mode normal display duty ratio partial display duty ratio division source osc in1 /osc in2 divider on/off cls normal/partial select dty partial division ratio comments 1/38 1/25 1/12 l(off) 1/38 1/25 1/12 osc in1 h(on) l (normal) ? 1/38 1/1 partial frame frequency: f oscin2 /4 /38 1/25 1/1 partial frame frequency: f oscin2 /4 /25 1/12 osc in2 l(off) 1/2 partial frame frequency: f oscin2 /2(division ratio) /4 /12 1/38 1/2 partial frame frequency: f oscin1 /2(division ratio) /4 /38 1/25 1/2 partial frame frequency: f oscin1 /2(division ratio) /4 /25 1/1 to 1/80 1/12 osc in1 h(on) h (partial) 1/4 partial frame frequency: f oscin1 /4(division ratio) /4 /12 1/38 1/25 l(off) 1/12 1/38 1/25 h(on) 1/12 osc in1 l (normal) ? 1/38 1/1 partial frame frequency: f oscin2 /4 /38 1/25 osc in2 l(off) 1/1 partial frame frequency: f oscin2 /4 /25 1/12 1/2 partial frame frequency: f oscin2 /2(division ratio) /4 /12 1/38 1/2 partial frame frequency: f oscin1 /2(division ratio) /4 /38 1/25 osc in1 h(on) 1/4 partial frame frequency: f oscin1 /4(division ratio) /4 /25 b/w gray = h 1/81 to 1/92 1/12 h (partial) 1/8 partial frame frequency: f oscin1 /8(division ratio) /4 /12 data sheet s15745ej2v0ds 26 pD16488A table 5-5 shows the relationship between the cls pin, resistors rn and rp, and the display clock circuit. table 5-5. relationship between cls pin/resistors and display clock circuit rn connection rp connection cls clock for normal display clock for partial display use example (figure 5-8) connected connected l internal oscillator internal oscillator (a) connected not connected h internal oscillator divided from oscillator clock (b) not connected connected l external clock internal oscillator (c) not connected not connected l external clock external clock (d) not connected not connected h external clock divided from external clock (e) figure 5-8. clock use examples r n r p r n f n f n r p f n f p osc in1 osc in2 osc out osc in1 osc in2 osc out osc in1 osc in2 osc out osc in1 osc in2 osc out osc in1 osc in2 osc out h or l open open h or l (a) (b) (c) (e) (d) data sheet s15745ej2v0ds 27 pD16488A figure 5-9. master/slave connection examples osc in1 osc sync osc sync (m/s = h) (m/s = l, cls = l) (m/s = h) (m/s = l, cls = h) osc in2 osc out osc in1 osc in2 osc out h or l open open (a) (b) master slave master slave data sheet s15745ej2v0ds 28 pD16488A 5.5 display timing generator the display clock generates timing signals for the line address circuit and the display data latch circuit. display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver output pins. reading of the display data is completely independent of the cpu's accessing of the display data ram. consequently, there are no adverse effects (such as flicker) on the lcd panel even when the display data ram is accessed asynchronously in relation to the lcd contents. the internal common timing is generated from the display clock. as shown in figure 5-10, a driver waveform based on the frame ac drive method is generated for the lcd driver. if a multiple set of pD16488A chips are used, the display timing signals (fr and fr sync ) for the slave side must be supplied from the master side. table 5-6. relationship between operation mode and fr, fr sync operation mode fr fr sync master (m/s = h) output output slave (m/s = l) input input data sheet s15745ej2v0ds 29 pD16488A figure 5-10. driver waveform based on frame ac drive method 12345678 90 91 92 90 91 92 1 2345678 1frame osc sync fr sync fr ram data v lcd v lc1 v lc2 v lc3 v lc4 v ss seg 1 v lcd v lc1 v lc2 v lc3 v lc4 v ss com 1 v lcd v lc1 v lc2 v lc3 v lc4 v ss com 2 v lcd v lc1 v lc2 v lc3 v lc4 v ss com 92 data sheet s15745ej2v0ds 30 pD16488A 5.6 power supply circuit the power supply circuit supplies the voltage needed to drive the lcd. it includes a booster, voltage regulator, and voltage follower. in the power supply circuit, the power system control register 1 (r32) is used to control the on/off status of the power supply circuit's booster, voltage regulator (also called v regulator), and voltage follower (v/f). this makes it possible to jointly use an external power supply together with certain functions of the on-chip power supply. table 5-7 shows the function that controls the 3-bit data in the power system control register 1 (r32) and table 5-8 shows a reference chart of combinations. table 5-7. control values of bits in power system control 1 status item 10 op2 booster control bit on off op1 voltage regulator (v regulator) control bit on off op0 voltage follower (v/f) control bit on off table 5-8. reference chart of combinations external use status op2 op1 op0 booster v regulator v/f power supply input boost-related note system pins <1> use on-chip power supply 1 1 1 enable enable enable v dd2 used <2> use v regulator and v/f only 0 1 1 disable enable enable v out not connected <3> use v/f only 0 0 1 disable disable enable v out , amp out not connected 0 0 0 disable disable disable v out , not connected <4> use external power supply only v lcd to v lc4 note the boost-related system pins are indicated as pins c1 + , c1 ? to c9 + , c9 ? , and c1a. 5.6.1 booster a booster that boosts the lcd driving voltage by 2 to 9 times is incorporated in the power supply circuit. since the booster uses signals from the on-chip oscillator, either the oscillator must be operating or a display clock must be input from an external source. the booster uses pins c1 + , c1 ? ? ? ? to c9 + , c9 ? ? ? ? for normal boost and pins c1a and v dd2 for boost regulation. the wire impedance should be kept as low as possible. the number of boost levels is set using the fbs2, fbs1, and fbs0 flags in the power system control 3 (r34), as shown in table 5-9. caution if a capacitor is connected to a boost-related system pin that is not for one of these set boost levels, current consumption may increase. therefore, do not connect any capacitors beyond the number of set boost levels. this also applies for the ca1 pin, used to regulate the boost levels. figure 5-11 describes the connection method for boost levels and capacitors. the partial booster is settings are made using the bst1 and bst0 flags in the power system control 3 (r34), as shown in table 5-10. data sheet s15745ej2v0ds 31 pD16488A figure 5-11. connection method for boost levels and capacitors c9 + c9 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 5-9. boost level settings for normal display's booster fbs2 fbs1 fbs0 boost level 000 4x 001 5x 010 6x 011 7x 100 8x 101 9x 1 1 0 prohibited 1 1 1 prohibited table 5-10. boost level settings for partial display's booster bst1 bst0 boost level 00 2x 01 3x 10 4x 1 1 prohibited data sheet s15745ej2v0ds 32 pD16488A 5.6.2 voltage regulator the boost voltage from v out is supplied to the voltage regulator and output as the lcd drive voltage v lcd . since the pD16488A has a 256-step electronic volume function and an on-chip resistor for v lcd voltage regulation, a small number of components can be used to configure a highly accurate voltage regulator. (1) when using an on-chip resistor for v lcd voltage regulation the on-chip resistor for v lcd voltage regulation and the electronic volume function can be used to regulate the contrast of the lcd contents by controlling the lcd drive voltage v lcd using commands only. in such cases, no external resistor is needed. if v lcd < v out , then the value for v lcd can be determined from the following equation. example equation v lcd < v out v lcd = (1 + ra rb ) v ev v lcd = (1 + ra rb ) (1 ? 384 ) v reg remark v ev = (1 ? 384 ) v reg figure 5-12. when using on-chip resistor for v lcd voltage regulation + - rb ra v lcd v ev (constant voltage source + electronic volume) v reg is the ic's on-chip constant voltage source, for which three types of temperature characteristic curves are available. these temperature characteristic curves can be adjusted via settings in the power system control register 1 (r32) (tsc1, tcs0), as shown in table 5-11. table 5-11 shows the v reg voltage when t a = 25 c. table 5-11. v reg voltage when t a = 25 c status tcs1 tcs0 temperature curve (%/ c) v reg (typ.) (v) internal power supply 0 0 ? 0.06 1.04 01 ? 0.08 0.98 10 ? 0.09 0.93 11 ? 0.12 0.85 is the electronic volume register (r35) value. any of 256 statuses can be set as the fetched status for corresponding to the data set to the 8-bit electronic control register. values based on settings in the electronic volume register (r35: normal display mode) and the partial electronic volume register (r36: partial display mode) are listed in table 5-12. data sheet s15745ej2v0ds 33 pD16488A table 5-12. values based on settings in electronic volume register register ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0 pev7 pev6 pev5 pev4 pev3 pev2 pev1 pev0 00000000 384 00000001 254 00000010 253 00000011 252 :: 11111101 2 11111110 1 11111111 0 rb/ra is an on-chip resistance factor used for the v lcd voltage regulator. this factor can be controlled at eight levels based on settings in power control register 2 (r33) (vrr2, vrr1, vrr0: normal display mode and pvr2, pvr1, pvr0: partial display mode). reference voltage values (1 + rb/ra) are determined based on 4-bit data set to v lcd 's on-chip resistance factor register, as shown in table 5-13. table 5-13. determination of reference voltage values based on settings of on-chip resistor for v lcd voltage regulation register vrr2 vrr1 vrr0 pvr2 pvr1 pvr0 1+rb/ra 000 5 001 8 010 12 011 13 100 16 101 19 110 21 111 24 data sheet s15745ej2v0ds 34 pD16488A (2) when using an external resistor (instead of using the on-chip resistor for v lcd voltage regulation) instead of using only the on-chip resistor setting for v lcd voltage regulation (irs = l), resistors (ra', rb' and rc') can be added between v ss and v r , between amp outp and amp out , and between v r and amp out to set the lcd drive voltage v lcd . in such cases, the electronic volume function can be used to control the lcd drive voltage v lcd and to regulate the contrast of the lcd contents via commands. in addition, the pD16488A enable selection between two display values (for normal display and partial display). the value is set using an external division resistor and is automatically selected by the dty flag in the control register 2 (r1). the v lcd value can be determined using example 1 (dty = 0) and example 2 (dty = 1) if it is within the range of v lcd < v out . example 1. dty = 0, normal display mode v lcd = (1 + a r b r ) v ev v lcd = (1 + a r b r ) (1 ? 384 ) v reg remark v ev (1 ? 384 ) v reg example 2. dty = 1, partial display mode v lcd = (1+ rc) b (r a r rc b r + ) v ev v lcd = (1+ () rc b r a r rc b r + ) (1 ? 384 ) v reg remark v ev = (1 ? 384 ) v reg figure 5-13. when using external resistor + - rb' rc ra' v lcd amp out v r amp outp normal/partial v lc1 regulation select circuit normal display mode partial display mode ab a b (dty = 0) a b (dty = 1) data sheet s15745ej2v0ds 35 pD16488A 5.6.3 use of op amp for level power supply control although the pD16488A includes a circuit designed for low power consumption (hpm1, hpm0 = 0, 0), display quality problems may occur when a large-load lcd panel is used. in such cases, the display quality and power consumption level can be improved by setting. the hpm1 and hpm0 flags in the power system control register 1 (r32) to "0, 1" to "1, 1" to switch to the op amp driver capacity for mode settings shown in table 5-14. check the actual display quality before deciding which mode to set. if setting high power mode still does not sufficiently improve the display quality, the lcd drive voltage must be provided from an external power source. table 5-14. op amp mode setting hpm1 hpm0 mode setting 0 0 normal mode 0 1 low power mode 1 0 high power mode 1 1 for power on mode data sheet s15745ej2v0ds 36 pD16488A 5.6.4 application examples of power supply circuits figures 5-14 to 5-19 show application examples of power supply circuits. figure 5-14. irs = h, [op2, op1, op0] = [1, 1, 1] c1 + c2 + c3 + c4 + c5 + c6 + c7 + c8 + c9 + c1 - c2 - c3 - c4 - c5 - c6 - c9 c1a - c7 - c8 - v dd1 v dd2 v out v rs v r open amp outp amp out v lcd v lc1 v lc2 v lc3 v lc4 v ss 9x boost mode figure 5-15. irs = l, [op2, op1, op0] = [1, 1, 1] rc ra' rb' c1 + c2 + c3 + c4 + c5 + c6 + c7 + c8 + c9 + c1 - c2 - c3 - c4 - c5 - c6 - c9 c1a - c7 - c8 - v dd1 v dd2 v out v rs v r amp outp amp out v lcd v lc1 v lc2 v lc3 v lc4 v ss 9x boost mode data sheet s15745ej2v0ds 37 pD16488A figure 5-16. irs = h, [op2, op1, op0] = [0, 1, 1] c1 + c2 + c3 + c4 + c5 open + c6 + c7 + c8 + c9 + c1 - c2 - c3 - c4 - c5 - c6 - c9 c1a - c7 - c8 - v dd1 v dd2 v out v rs v r open open amp outp amp out v lcd v lc1 v lc2 v lc3 v lc4 v ss figure 5-17. irs = l, [op2, op1, op0] = [0, 0, 1] c1 + c2 + c3 + c4 + c5 + c6 + c7 + c8 + c9 + c1 - c2 - c3 - c4 - c5 - c6 - c9 c1a - c7 - c8 - v dd1 v dd2 v out v rs v r amp outp amp out v lcd v lc1 v lc2 v lc3 v lc4 v ss open open open open data sheet s15745ej2v0ds 38 pD16488A figure 5-18. irs = l, [op2, op1, op0] = [0, 0, 0] c1 + c2 + c3 + c4 + c5 + c6 + c7 + c8 + c9 + c1 - c2 - c3 - c4 - c5 - c6 - c9 c1a - c7 - c8 - v dd1 v dd2 v out v rs v r amp outp amp out v lcd v lc1 v lc2 v lc3 v lc4 v ss open open open figure 5-19. master/slave connection example c1 + c2 + c3 + c4 + c5 + c6 + c7 + c8 + c9 + c1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? master slave open open open open v lcd v lc1 v lc2 v lc3 v lc4 v rs v r amp outp amp out data sheet s15745ej2v0ds 39 pD16488A 5.7 lcd display drivers pD16488A includes a full dot driver. the full dot driver has a 33-level gray-scale palette (eight levels of pulse width modulation plus four-frame rate control), from which four levels of gray scale can be selected and registered as the ic's output gray-scale palette (refer to 6.23 gary scale registers 1 to 4 (r23 to r26) ). 5.7.1 full-dot pulse width modulation the pD16488A's pulse width modulator divides the normal lcd display signal's segment pulse width by eight and outputs in synch with the dot output timing based on the ratio (1/8 to 8/8 pulses) for the gray-scale palette that has been selected via a command. figure 5-20. full-dot pulse width modulation 12345678 90 91 92 90 91 92 12345678 1/8 4/8 6/8 8/8 23 1 v lcd v lc1 v lc2 v lc3 v lc4 v ss seg 1 v lcd v lc1 v lc2 v lcd v lc1 v lc2 v lc3 v lc4 v ss com 1 1 frame enlarged section caution there is no pulse width modulation for common outputs. data sheet s15745ej2v0ds 40 pD16488A the output pulses are output as odd-numbered lines/even-numbered lines or as even-numbered lines/odd-numbered lines, as shown in figure 5-21. the pulse rising edge and falling edge combinations for each frame are listed in table 5-15. figure 5-21. example of pulse width modulated output 123456789101112 12345678 8/8 4/8 3/8 8/8 8/8 4/8 1 3 v lcd v lc1 v lc2 v lc3 v lc4 v ss 1 frame 90 91 92 2 data sheet s15745ej2v0ds 41 pD16488A table 5-15. example of pulse width modulated output (1/3) gray-scale com 1, 2 frames 3, 4 frames 5, 6 frames 7, 8 frames level seg odd numbered seg even numbered seg odd numbered seg even numbered seg odd numbered seg even numbered seg odd numbered seg even numbered 04n+100000000 4n+200000000 4n+300000000 4n+400000000 1 4n+1 1 1000000 4n+2 0 0 0 0 1 10 0 4n+3000000 1 1 4n+4 0 0 1 10000 2 4n+1 1 10 0 1 10 0 4n+2 1 10 0 1 10 0 4n+3 0 0 1 10 0 1 1 4n+4 0 0 1 10 0 1 1 3 4n+1 1 1 1 1 1 10 0 4n+2 1 10 0 1 1 1 1 4n+3 1 1 1 10 0 1 1 4n+4 0 0 1 1 1 1 1 1 4 4n+1 1 1 1 1 1 1 1 1 4n+2 1 1 1 1 1 1 1 1 4n+3 1 1 1 1 1 1 1 1 4n+4 1 1 1 1 1 1 1 1 5 4n+1 2 2 1 1 1 1 1 1 4n+2 1 1 1 1 2 2 1 1 4n+3 1 1 1 1 1 1 2 2 4n+4 1 1 2 2 1 1 1 1 6 4n+1 2 2 1 1 2 2 1 1 4n+2 2 2 1 1 2 2 1 1 4n+3 1 1 2 2 1 1 2 2 4n+4 1 1 2 2 1 1 2 2 7 4n+1 2 2 2 2 2 2 1 1 4n+2 2 2 1 1 2 2 2 2 4n+3 2 2 2 2 1 1 2 2 4n+4 1 1 2 2 2 2 2 2 8 4n+1 2 2 2 2 2 2 2 2 4n+2 2 2 2 2 2 2 2 2 4n+3 2 2 2 2 2 2 2 2 4n+4 2 2 2 2 2 2 2 2 9 4n+1 3 3 2 2 2 2 2 2 4n+2 2 2 2 2 3 3 2 2 4n+3 2 2 2 2 2 2 3 3 4n+4 2 2 3 3 2 2 2 2 10 4n+1 3 3 2 2 3 3 2 2 4n+2 3 3 2 2 3 3 2 2 4n+3 2 2 3 3 2 2 3 3 4n+4 2 2 3 3 2 2 3 3 remarks 1. n: integer from 0 to 31. 2. a: rising edge of pulse during line a output. 3. a: rising edge of pulse at start of line a output. 4. a: pwm pulse width (a/8) data sheet s15745ej2v0ds 42 pD16488A table 5-15. example of pulse width modulated output (2/3) gray-scale com 1, 2 frames 3, 4 frames 5, 6 frames 7, 8 frames level seg odd numbered seg even numbered seg odd numbered seg even numbered seg odd numbered seg even numbered seg odd numbered seg even numbered 11 4n+1 3 3 3 3 3 3 2 2 4n+2 3 3 2 2 3 3 3 3 4n+3 3 3 3 3 2 2 3 3 4n+4 2 2 3 3 3 3 3 3 12 4n+1 3 3 3 3 3 3 3 3 4n+2 3 3 3 3 3 3 3 3 4n+3 3 3 3 3 3 3 3 3 4n+4 3 3 3 3 3 3 3 3 13 4n+1 4 4 3 3 3 3 3 3 4n+2 3 3 3 3 4 4 3 3 4n+3 3 3 3 3 3 3 4 4 4n+4 3 3 4 4 3 3 3 3 14 4n+1 4 4 3 3 4 4 3 3 4n+2 4 4 3 3 4 4 3 3 4n+3 3 3 4 4 3 3 4 4 4n+4 3 3 4 4 3 3 4 4 15 4n+1 4 4 4 4 4 4 3 3 4n+2 4 4 3 3 4 4 4 4 4n+3 4 4 4 4 3 3 4 4 4n+4 3 3 4 4 4 4 4 4 16 4n+1 4 4 4 4 4 4 4 4 4n+2 4 4 4 4 4 4 4 4 4n+3 4 4 4 4 4 4 4 4 4n+4 4 4 4 4 4 4 4 4 17 4n+1 5 5 4 4 4 4 4 4 4n+2 4 4 4 4 5 5 4 4 4n+3 4 4 4 4 4 4 5 5 4n+4 4 4 5 5 4 4 4 4 18 4n+1 5 5 4 4 5 5 4 4 4n+2 5 5 4 4 5 5 4 4 4n+3 4 4 5 5 4 4 5 5 4n+4 4 4 5 5 4 4 5 5 19 4n+1 5 5 5 5 5 5 4 4 4n+2 5 5 4 4 5 5 5 5 4n+3 5 5 5 5 4 4 5 5 4n+4 4 4 5 5 5 5 5 5 20 4n+1 5 5 5 5 5 5 5 5 4n+2 5 5 5 5 5 5 5 5 4n+3 5 5 5 5 5 5 5 5 4n+4 5 5 5 5 5 5 5 5 21 4n+1 6 6 5 5 5 5 5 5 4n+2 5 5 5 5 6 6 5 5 4n+3 5 5 5 5 5 5 6 6 4n+4 5 5 6 6 5 5 5 5 remarks 1. n: integer from 0 to 31. 2. a: rising edge of pulse during line a output. 3. a: rising edge of pulse at start of line a output. 4. a: pwm pulse width (a/8) data sheet s15745ej2v0ds 43 pD16488A table 5-15. example of pulse width modulated output (3/3) gray-scale com 1, 2 frames 3, 4 frames 5, 6 frames 7, 8 frames level seg odd numbered seg even numbered seg odd numbered seg even numbered seg odd numbered seg even numbered seg odd numbered seg even numbered 22 4n+1 6 6 5 5 6 6 5 5 4n+2 6 6 5 5 6 6 5 5 4n+3 5 5 6 6 5 5 6 6 4n+4 5 5 6 6 5 5 6 6 23 4n+1 6 6 6 6 6 6 5 5 4n+2 6 6 5 5 6 6 6 6 4n+3 6 6 6 6 5 5 6 6 4n+4 5 5 6 6 6 6 6 6 24 4n+1 6 6 6 6 6 6 6 6 4n+2 6 6 6 6 6 6 6 6 4n+3 6 6 6 6 6 6 6 6 4n+4 6 6 6 6 6 6 6 6 25 4n+1 7 7 6 6 6 6 6 6 4n+2 6 6 6 6 7 7 6 6 4n+3 6 6 6 6 6 6 7 7 4n+4 6 6 7 7 6 6 6 6 26 4n+1 7 7 6 6 7 7 6 6 4n+2 7 7 6 6 7 7 6 6 4n+3 6 6 7 7 6 6 7 7 4n+4 6 6 7 7 6 6 7 7 27 4n+1 7 7 7 7 7 7 6 6 4n+2 7 7 6 6 7 7 7 7 4n+3 7 7 7 7 6 6 7 7 4n+4 6 6 7 7 7 7 7 7 28 4n+1 7 7 7 7 7 7 7 7 4n+2 7 7 7 7 7 7 7 7 4n+3 7 7 7 7 7 7 7 7 4n+4 7 7 7 7 7 7 7 7 29 4n+1 8 8 7 7 7 7 7 7 4n+2 7 7 7 78 8 7 7 4n+3 7 7 7 7 7 78 8 4n+4 7 78 8 7 7 7 7 30 4n+1 8 8 7 78 8 7 7 4n+2 8 8 7 78 8 7 7 4n+3 7 78 8 7 78 8 4n+4 7 78 8 7 78 8 31 4n+1 8 8 8 8 8 8 7 7 4n+2 8 8 7 78888 4n+3 8 8 8 8 7 78 8 4n+4 7 7888888 32 4n+1 8 8 8 8 8 8 8 8 4n+2 8 8 8 8 8 8 8 8 4n+3 8 8 8 8 8 8 8 8 4n+4 8 8 8 8 8 8 8 8 remarks 1. n: integer from 0 to 31. 2. a: rising edge of pulse during line a output. 3. a: rising edge of pulse at start of line a output. 4. a: pwm pulse width (a/8) data sheet s15745ej2v0ds 44 pD16488A 5.7.2 full-dot frame rate control when combined with pulse width modulation as described in table 5-15, the pD16488A's frame speed is based on 8- frame cycles. the subsampling pattern is output based on the palette stored in the ic. full-dot gray-scale palette (output pulse width: x/8 pulses) frames gray scale 12345678 comments level 0 00000000off data level 1 11000000 level 2 11001100 level 3 11111100 level 4 11111111 level 5 22111111 level 6 22112211 level 7 22222211 level 8 22222222 level 9 33222222 level 10 33223322 level 11 33333322 level 12 33333333 level 13 44333333 level 14 44334433 level 15 44444433 level 16 4444444450% level 17 55444444 level 18 55445544 level 19 55555544 level 20 55555555 level 21 66555555 level 22 66556655 level 23 66666655 level 24 66666666 level 25 77666666 level 26 77667766 level 27 77777766 level 28 77777777 level 29 88777777 level 30 88778877 level 31 88888877 level 32 88888888 100% remark the gradation in the comments column are images of the gray-scale level. data sheet s15745ej2v0ds 45 pD16488A 5.7.3 line shift driver if the frame rate control is performed with equal pulse widths and the same gray scale is displayed on the lcd's full screen, problems such as flickering may occur on the lcd panel. the pD16488A provides a line shift driver as a countermeasure against such screen image problems. using 8 frames per cycle, the segment pwm output timing is shifted among the common outputs, as shown in table 5-16 below. table 5-16. line shift driver turn 1 turn 2 frame 12345678123456781234 com 1 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 com 2 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 com 3 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 com 4 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 com 5 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 com 6 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 com 7 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 com 8 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 com 9 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 com 10 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 f1 f2 f3 f4 f5 f6 f7 f8 ? ???????????????????? remark fx: pulse width modulated output frame (see 5.7.2 full-dot frame rate control ). figure 5-22. full dot frame rate control 12345 1 2 15 3 1 7 3 7 5 6 2 8 15 3 1 7 3 7 5 6 2 8 15 3 1 7 3 7 5 6 2 8 15 3 1 7 3 7 5 6 2 8 15 3 1 7 3 7 5 6 2 8 on off on off on off on off on off on off on off seg 1 seg 2 seg 3 seg 4 seg 5 com 1 com 2 com 3 com 4 com 5 com 91 com 92 first frame second frame 91 92 remark numerical values in the segment data correspond to the gray-scale palette's frame numbers. data sheet s15745ej2v0ds 46 pD16488A figure 5-23. line shift driver image seg 1 seg 3 seg 5 seg 7 seg 127 seg 2 seg 4 seg 6 seg 8 seg 126 seg 128 seg 1 seg 3 seg 5 seg 7 seg 127 seg 2 seg 4 seg 6 seg 8 seg 126 seg 128 com 1 com 2 com 3 com 4 com 5 com 90 com 91 com 92 com 1 com 2 com 3 com 4 com 5 com 90 com 91 com 92 f1 f5 f3 f7 f1 f5 f3 f7 f2 f6 f4 f8 f2 f6 f4 f8 turn 1, first frame turn 1, second frame data sheet s15745ej2v0ds 47 pD16488A 5.7.4 display size settings the pD16488A can be set for any duty value from 1/1 to 1/92. this duty setting can be made via bits dt6 to dt0 in the duty setting register (r5), as shown in table 5-17. table 5-17. duty settings dt6dt5dt4dt3dt2dt1dt0 duty 0000000 1/1 0000001 1/2 0000010 1/3 0000011 1/4 :: 1011001 1/90 1011010 1/91 1011011 1/92 1011100prohibited caution the duty setting can not be over 1/92 duty (5ch). if 1/92 duty is exceeded, operation is not guaranteed. 5.7.5 setting of lcd ac driver's inversion cycle and ac driver's inversion position the pD16488A enable any setting to be made for the ac driver's inversion position and the inversion position shift amount for each displayed frame via settings made in the ac driver inversion cycle register (r6) and the ac driver inversion position shift register (r7) for normal display mode or via settings made in the partial ac driver inversion cycle register (r8) and the partial ac driver inversion position shift register (r9) for partial display mode. in normal display mode, the ac driver inversion cycle can be set for any number of inverted (reverse display) lines listed in table 5-18, based on the nid6 to nid0 bit settings in the ac driver inversion cycle register (r6). if the screen display size has been changed via settings made in the duty setting register (r5), the nidn values are automatically overwritten by values from the corresponding dtyn bits. the shift amount for each displayed frame can be set as shown in table 5-19 via settings made to bits msd6 to msd0 in the ac driver inversion position shift register (r7). table 5-18. settings of ac driver inversion cycle register (r6) nid6 nid5 nid4 nid3 nid2 nid1 nid0 inverted lines 0000000 1 0000001 2 0000010 3 0000011 4 :: 1011001 90 1011010 91 1011011 92 1011100 prohibited caution the inversion line can not be over 92-inversion line (5ch). if 92-inversion line is exceeded, operation is not guaranteed. data sheet s15745ej2v0ds 48 pD16488A table 5-19. settings of ac driver inversion position shift register msd6 msd5 msd4 msd3 msd2 msd1 msd0 inversion position shift amount 0000000 0 0000001 1 0000010 2 0000011 3 :: 1011001 89 1011010 90 1011011 91 1011100 prohibited caution the inversion position shift amount can not be over 91 (5ch). if 91 is exceeded, operation is not guaranteed. in partial display mode, the ac driver inversion cycle can be set for any number of inverted (reverse display) lines listed i n table 5-20, based on the pid5 to pid0 bit settings in the partial ac driver inversion cycle register (r8). the shift amount for each displayed frame can be set as shown in table 5-21 via settings made to bits psd5 to psd0 in the partial ac driver inversion position shift register (r9). table 5-20. settings of partial ac driver inversion cycle register (r8) pid5 pid4 pid3 pid2 pid1 pid0 inverted lines 000000 1 000001 2 000010 3 000011 4 :: 100011 36 100100 37 100101 38 table 5-21. setting of partial ac driver inversion position shift register (r9) psd5 psd4 psd3 psd2 psd1 psd0 inversion position shift amount 000000 0 000001 1 000010 2 000011 3 :: 100011 35 100100 36 100101 37 be sure to maintain the following relationship among the display size, ac inversion cycle, and ac inversion position. display size (duty) ac inversion cycle ac inversion shift amount caution setting a small inversion cycle will cause a reduction in the ic's display drive capacity and an increase in the current consumption. we therefore recommend determining the inversion cycle after making a thorough evaluation of the actual lcd panel. data sheet s15745ej2v0ds 49 pD16488A 5.8 display modes 5.8.1 partial display mode the pD16488A includes a function for outputting a display that uses only part of the lcd panel. the duty setting for partial display mode can be selected as 1/12, 1/25, or 1/38. parts of the lcd panel that are outside of the specified display area are scanned with non-select waveforms. the partial start line address register (r21) is used to select which part of the lcd panel to use for the partial display. the display area starts from the start line address and includes the number of lines (12, 25, or 38 lines) that has been specified via the partial display mode setting (r10). when entering this mode, the booster is set to the boost level number that has been set via the power system control register 3 (partial display boost register) (r34) and the display start line is fixed as 00h. in addition, the bias level is automatically changed to the value that has been set via the partial display mode setting (r10). the relationship between the oscillator's frequency and the frame frequency in partial mode is also automatically changed. figure 5-24 shows the mutual relationship between the partial line start address and the lcd display. when using the partial display mode, the blinking and reverse display functions can be used in the same way as during full-dot display mode. caution the lcd driver voltage is lower in partial display mode, because the duty is lower than in normal display mode. there may be restrictions on the usable duty depending on the lcd panel characteristics. we recommend determining the partial duty after making a thorough evaluation of the actual lcd panel. figure 5-24. relationship between partial line start address and lcd display (in partial display mode) 00h 01h 02h 03h 1dh 1eh 1fh ... display start line (00h) partial display start line 12, 25, or 38 lines non-display areas caution in partial display mode, the display start line setting register (r12) command is ignored. when switching from normal display mode to partial display mode or from partial display mode to normal display mode, if an electric charge remains in the smoothing capacitor that is connected between the lcd drive voltage pins (v lcd , v lc1 to v lc4 ) and the v ss pin, troubles such as a brief all-black display may occur during the mode switching operation. to avoid such troubles, we recommend using the following power-on sequence. data sheet s15745ej2v0ds 50 pD16488A (1) normal display partial display switch sequence disp = 0 r0 display off hpm1 = 1, hpm0 = 0 r32 high power mode settings switch display mode r1 control register 2: switch dty flag wait time 700 ms (stabilization time for lcd drive voltage and booster) note hpm1 = x, hpm0 = x r32 high power mode settings (to mode used during normal display) disp = 1 r0 display on, internal operations status note this 700 ms wait time indicates the time for the v lcd level to change from 15 v to 6 v and thus varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. we recommend determining the wait time after making a thorough evaluation of the actual device. (2) partial display normal display switch sequence disp = 0 r0 display off hpm1 = 1, hpm0 = 1 r32 power on mode settings switch display mode r1 control register 2: switch dty flag wait time 400 ms (stabilization time for lcd drive voltage and booster) note hpm1 = x, hpm0 = x r32 high power mode settings (to mode used during normal display) disp = 1 r0 display on, internal operations status note this 400 ms wait time indicates the time for the v lcd level to change from 6 v to 15 v and thus varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. we recommend determining the wait time after making a thorough evaluation of the actual device. data sheet s15745ej2v0ds 51 pD16488A 5.8.2 monochrome (black/white) display the pD16488A provides both a four-level gray scale display mode and a monochrome display mode. to switch to the monochrome display mode, set gray = h. the display ram for one screen of monochrome display mode contents is configured as 128 bits x 128 bits (16 x 8 bits). when using these ic's in monochrome display mode, two screens of data can be written to the display ram and the two screens can be switched by setting the dsel bit in the control register 2 (r1). screen 1 is displayed on the lcd panel when dsel = l and screen 2 is displayed when dsel = h. when writing data, the display ram uses the same x address (00h to 0fh) and y address and the bww bit value in the control register 2 (r1) determines which of the two screens the data will be written to: when bww = l, data is written to screen 1 and when bww = h, data is written to screen 2, as shown in figure 5-25. when accessing a specified bit, specify both the x address and y address. the display data in d 0 to d 7 (sent from the cpu) corresponds to the segx portions of the lcd display, as shown in figure 5-26. figure 5-27 shows the relationship between the display data in monochrome display mode and the page/column addresses. figure 5-25. display ram image in monochrome (black/white) mode 00h 0fh 0fh 00h screen 1 dsel = l (during display) bww = l (during write) screen 2 dsel = h (during display) bww = h (during write) figure 5-26. relationship between display data and lcd display 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data display data lcd display data sheet s15745ej2v0ds 52 pD16488A figure 5-27. relation between the display data and x/y address (in monochrome display mode) com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com30 com31 d4 data x address d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h com33 21h com34 22h com35 23h com36 24h com37 25h com38 76h com83 77h com84 78h com85 79h com86 7ah com87 7bh com88 7ch com89 7dh com90 7eh com91 7fh com92 0 d0 1 d0 seg1 seg2 seg3 seg4 seg5 seg6 01h 02h 7dh 03h 01h 0fh 1 1 0 1 seg128 seg125 seg126 seg127 7fh 00h 7eh 7dh seg7 seg8 7ch 04h 07h 7bh 05h 7ah 06h 79h 78h 7fh 00h 0 0 0 0 adc 7ch 03h 7eh 01h 02h 00h 0 0 0 0 0 1 1 com output yaddress start column address lcd output com27 com28 com29 com32 com9 com10 com11 com12 com13 com14 com3 com4 com5 com6 com7 com8 com1 com2 92-line data sheet s15745ej2v0ds 53 pD16488A 5.9 reset in the pD16488A, a reset is executed when the /res input is at low level or when a reset command is entered. the ic is reset to its default settings. these default settings are listed in the table below. register number /res reset command control register 1 r0 enabled (disp flag only) enabled control register 2 r1 enabled (idis flag only) x address register r3 disabled y address register r4 duty setting register r5 enabled note2 ac driver inversion cycle register r6 ac driver inversion position shift register r7 enabled partial ac driver inversion cycle register r8 partial ac driver inversion position shift register r9 partial display mode setting register r10 display memory access register note1 r11 disabled display start line setting register r12 enabled blink x address register r13 blink start line address register r14 blink end line address register r15 blink data memory access register note1 r16 disabled inverted x address register r17 enabled inversion start line address register r18 inversion end line address register r19 inverted data memory access register note1 r20 disabled partial start line address register r21 enabled gray scale data register 1 (0, 0) r23 gray scale data register 2 (0, 1) r24 gray scale data register 3 (1, 0) r25 gray scale data register 4 (1, 1) r26 partial gray scale data register 1 (0, 0) r27 partial gray scale data register 2 (0, 1) r28 partial gray scale data register 3 (1, 0) r29 partial gray scale data register 4 (1, 1) r30 power system control register 1 r32 power system control register 2 r33 power system control register 3 r34 electronic volume register r35 partial electronic volume register r36 boost adjustment register r37 ram test mode setting register r44 signature read register r45 disabled enabled: default value is input, disabled: default value is not input notes 1. when using the /res pin to reset, the contents of memory are not retained. use the reset command to reset if the memory contents need to be retained. 2. be sure to set this register again after input the reset command. cautions 1. using the /res pin to reset initializes the shift clock counter. 2. always input the reset command as the first command after power on. data sheet s15745ej2v0ds 54 pD16488A 6. command registers the pD16488A uses a combination of rs, /rd (e), and /wr (r,/w) signals to identify data bus signals. command interpretation and execution is performed using internal timing that does not depend on any external clock. therefore, processing is very fast and there is usually no need to check for a busy status. the i80 series cpu interface activates read commands using a low pulse input to the /rd pin and activates write commands using a low pulse input to the /wr pin. the m68 series cpu interface sets read mode using a high level input to the r,/w pin and sets write mode using a low level input to the same pin. it activates both read and write commands using a high-level pulse input to the e pin. command descriptions using an i80 series cpu interface are shown as follows. the m68 series cpu interface differs from the i80 series cpu interface in that /rd (e) is at high level during status read and display data read operations, as shown in the following command descriptions and command table. if the serial interface has been selected, data is input sequentially starting from d 7 . data sheet s15745ej2v0ds 55 pD16488A 6.1 control register 1 (r0) this command specifies the pD16488A's general operation modes. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 rmw disp stby bld ivd halt adc comr flag function rmw 0: address is incremented after both write access and read access. 1: read/modify/write mode (address is incremented only after write access) disp 0: display off (all lcd output pins output the v ss level and oscillator and dc/dc converter are operating) 1: display on stby 0: normal operation 1: internal operation and oscillation are stopped. display is off. bld the blinking dots are specified via the blink start/end line address registers and data is set to blink data ram. 0: stop blinking 1: start blinking ivd the number of inverted dots is specified via the inversion start/end line address registers and data is set to inverted data ram. 0: stop inversion 1: start inversion halt 0: start internal operation 1: stop internal operation (since different display modes are used, when switching between partial and normal display modes, the lcd output pins all output the v ss level and the oscillator is operating, but the dc/dc converter is stopped) adc note the column address corresponding to the seg outputs (see table 6-1 ) for displaying the contents of the display data ram. comr note this inverts (reverses) the scan direction for common outputs. (see table 6-2 ) note the reset command must be executed before changing this flag's setting. table 6-1. relationship between display ram column address and seg outputs seg output seg 1 seg 128 0 00h column addresses 7fh adc (d 1 ) 17fh column addresses 00h table 6-2. relationship between common scan circuit and scan direction com output scan direction 0com 1 com 92 comr (d 0 ) 1com 92 com 1 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 data sheet s15745ej2v0ds 56 pD16488A 6.2 control register 2 (r1) this command specifies the pD16488A's general operation modes. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 110fdm ?? dsel bww gray dty inc flag function fdm settings for full screen display mode 0: normal operation 1: full screen display (set entire screen to on) (when using four-level gray scale, gray-scale level 32 is output for full screen display). dsel selects display screen during monochrome display mode. 0: screen 1 1: screen 2 bww selects data write screen during monochrome display mode. 0: screen 1 1: screen 2 gray note 0: 4-level gray scale display mode 1: monochrome display mode dty note 0: normal display mode (1/1 to 1/128 duty) 1: partial display mode (1/12, 1/25, or 1/38 duty, 1/5 or 1/6 bias) inc 0: increments x address at each access 1: increments y address at each access note the halt command must be executed before changing this flag's setting. table 6-3. relationship between ic's functions and display modes item normal display mode (dty = 0) partial display mode (dty = 1) duty 1/1 to 1/92 duty ? 1/12, 1/25, or 1/38 duty booster 4, 5, 6, 7, 8, 9 ? 2, 3, 4 bias level 1/11, 1/12, 1/10, 1/9, 1/8, 1/7 ? 1/5, 1/6 gray scale data uses levels set to the gray scale data registers (r23 to r26) ? uses levels set to the partial gray scale data registers (r27 to r30) (1+rb/ra) v lcd regulator resistance factor uses values of vrr2 to vrr0 in the power system control register 2 (r33) ? uses values of pvr2 to pvr0 in the power system control register 2 (r33) electronic volume uses value from the electronic volume register (r35) ? uses value from the partial electronic volume register (r36) default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 data sheet s15745ej2v0ds 57 pD16488A 6.3 reset command (r2) when this command is input, the ic's registers (r0 to r44) are reset to their initial values. however, the contents of memory are retained. always input the reset command as the first command after power application. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 100000001 6.4 x address register (r3) the x address register specifies the x address in the display ram accessed by the cpu. this address is automatically incremented each time the display ram is accessed (inc = 0, rmw = 0). rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ??? xa4 xa3 xa2 xa1 xa0 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ??? 00000 6.5 y address register (r4) the y address register specifies the y address in the display ram accessed by the cpu. this address is automatically incremented each time the display ram is accessed (inc = 1, rmw = 0). rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ? ya6 ya5 ya4 ya3 ya2 ya1 ya0 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 ? data sheet s15745ej2v0ds 58 pD16488A 6.6 duty setting register (r5) the display duty can be set to any duty ratio between 1/1 and 1/92, as is shown in table 6-4. before modifying this register, be sure to use the halt command (control register 1 (r0)) to stop internal operations. also, be sure to set this register again after input the reset command. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ? dt6dt5dt4dt3dt2dt1dt0 table 6-4. duty setting register (r5) settings dt6dt5dt4dt3dt2dt1dt0 duty 0000000 1/1 0000001 1/2 0000010 1/3 0000011 1/4 :: 1011001 1/90 1011010 1/91 1011011 1/92 1011000inhibited caution the display size can not be over 1/92 duty ( 5ch). if 1/92 duty is exceeded, operation is not guaranteed. default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???????? data sheet s15745ej2v0ds 59 pD16488A 6.7 ac driver inversion cycle register (r6) the ac driver's line position for normal display mode can be set as shown in table 6-5. when a dtyn value is changed in the duty setting register (r5), the nidn value is automatically overwritten by the dtyn value . be sure to set this register again after input the reset command. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ? nid6 nid5 nid4 nid3 nid2 nid1 nid0 table 6-5. ac driver inversion cycle register (r6) settings nid6 nid5 nid4 nid3 nid2 nid1 nid0 inversion line 0000000 1 0000001 2 0000010 3 0000011 4 :: 1011001 90 1011010 91 1011011 92 1011100 inhibited caution the inversion line can not be over 92 (5ch). if 92-line is exceeded, operation is not guaranteed. default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???????? 6.8 ac driver inversion position shift register (r7) this register shifts the inversion position for each frame in normal display mode by the shift amount shown in table 6-6. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ? msd6 msd5 msd4 msd3 msd2 msd1 msd0 table 6-6. ac driver inversion position shift register (r7) settings msd5 msd5 msd4 msd3 msd2 msd1 msd0 inversion position shift amount 0000000 0 0000001 1 0000010 2 0000011 3 :: 1011001 89 1011010 90 1011011 91 1011100 92 caution the inversion position shift amount can not be over 91 (5ch). if 91 is exceeded, operation is not guaranteed. default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 data sheet s15745ej2v0ds 60 pD16488A 6.9 partial ac driver inversion cycle register (r8) the ac driver's line position can be set as shown in table 6-7. when a pdtn value is changed in the partial display mode setting register (r10), the pidn value is automatically overwritten by the pdtn value. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ?? pid5 pid4 pid3 pid2 pid1 pid0 table 6-7. partial ac driver inversion cycle register (r8) settings pid5 pid4 pid3 pid2 pid1 pid0 inversion line 000000 1 000001 2 000010 3 000011 4 :: 100011 36 100100 37 100101 38 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ?? 100101 6.10 partial ac driver inversion position shift register (r9) this register shifts the inversion position for each frame by the shift amount shown in table 6-8. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ?? psd5 psd4 psd3 psd2 psd1 psd0 table 6-8. partial ac driver inversion position shift register (r9) settings psd5 psd4 psd3 psd2 psd1 psd0 inversion position shift amount 000000 0 000001 1 000010 2 000011 3 :: 100011 35 100100 36 100101 37 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ??? 00000 data sheet s15745ej2v0ds 61 pD16488A 6.11 partial display mode setting register (r10) this command specifies the operation mode to be used in the pD16488A's partial display mode. before modifying this register, be sure to use the halt command (control register 1 (r0)) to stop internal operations. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ???? pbis ? pdt1 pdt0 flag function pbis sets bias level for partial display mode 0: 1/5 bias 1: 1/6 bias pdt1 pdt0 duty in partial display mode 0 0 1/38 duty 0 1 1/25 duty 1 0 1/12 duty pdt1, pdt0 1 1 prohibited caution with the setting of 1/12 duty, the level voltage (v lcn ) for driving liquid crystal pannel may not reach the set value depending on the panel used. thoroughly evaluate the relationship between the duty and driving voltage with the actual system. default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???? 0 ? 00 6.12 display memory access register (r11) the display memory access register is used when accessing the display ram. when this register is write-accessed, data is written directly to the display ram. when this register is read-accessed, data from the display ram is first latched to thi s register before being sent to the bus during the next read operation. accordingly, one dummy read access is required after display ram access has been set. when using reset command to reset, the contents of memory are retained. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???????? ? ? data sheet s15745ej2v0ds 62 pD16488A 6.13 display start line setting register (r12) display start line set specifies the top line in the display. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ? dsl6 dsl5 dsl4 dsl3 dsl2 dsl1 dsl0 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 6.14 blink x address register (r13) the blink x address register specifies the x address of the blink data ram accessed by the cpu. this address is automatically incremented each time the blink data ram is accessed. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ???? bxa3 bxa2 bxa1 bxa0 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???? 0000 6.15 blink start line address register (r14) the blink start line address register specifies the start line address of the display ram accessed when the cpu uses blink display mode. the range of blinking lines is determined based on the contents of this register and the blink end line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 ? bsl6 bsl5 bsl4 bsl3 bsl2 bsl1 bsl0 ? default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 6.16 blink end line address register (r15) the blink end line address register specifies the end line address of the display ram accessed when the cpu uses blink display mode. the range of blinking lines is determined based on the contents of this register and the blink start line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 ? bel6 bel5 bel4 bel3 bel2 bel1 bel0 ? default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 data sheet s15745ej2v0ds 63 pD16488A 6.17 blink data memory access register (r16) the blink data memory access register is used to access the blink data ram. when this register is write-accessed, data is written directly to the blink data ram. when using reset command to reset, the contents of memory are retained. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 data status 0normal 1 blink default settings (initial values set by reset command, all data) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 6.18 inverted x address register (r17) the inverted x address register specifies the x address in the inverted data ram accessed by the cpu. this address is incremented each time the inversion ram is accessed. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ???? ixa3 ixa2 ixa1 ixa0 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???? 0000 6.19 inversion start line address register (r18) the inversion start line address register specifies the start line address in the display ram accessed by the cpu when using reverse (inverted) display mode. the range of inverted lines is determined based on the contents of this register and the inversion end line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ? isl6 isl5 isl4 isl3 isl2 isl1 isl0 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 ? data sheet s15745ej2v0ds 64 pD16488A 6.20 inversion end line address register (r19) the inversion end line address register specifies the end line address in the display ram accessed by the cpu when using reverse (inverted) display mode. the range of inverted lines is determined based on the contents of this register and the inversion start line address register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 ? iel6 iel5 iel4 iel3 iel2 iel1 iel0 ? default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 6.21 inverted data memory access register (r20) the inverted data memory access register is used when accessing the inverted data ram. when this register is accessed, the data is written directly to the inverted data ram. when using reset command to reset, the contents of memory are retained. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? data status 0normal 1 inverted default settings (initial values set by reset command, all data) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 6.22 partial start line address register (r21) the partial start line address register specifies the start line address in the display ram accessed by the cpu when using partial display mode. the partial display area is determined as the number of lines specified in the partial display mode setting register (r10), starting from this start line address. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 ? psl6 psl5 psl4 psl3 psl2 psl1 psl0 ? default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 0000000 ? data sheet s15745ej2v0ds 65 pD16488A 6.23 gray scale data registers 1 to 4 (r23 to r26) the gray scale data registers specify the gray scale level when using normal four-level gray scale display mode. use of this register optimizes the gray scale display. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r23 0, 0 1 ?? gd5 gd4 gd3 gd2 gd1 gd0 ? r24 0, 1 1 ?? gd5 gd4 gd3 gd2 gd1 gd0 ? r25 1, 0 1 ?? gd5 gd4 gd3 gd2 gd1 gd0 ? r26 1, 1 1 ?? gd5 gd4 gd3 gd2 gd1 gd0 ? d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 gray scale level disable disable 000000 level 0 disable disable 000001 level 1 disable disable 000010 level 2 disable disable 000011 level 3 :: disable disable 011111 level 31 disabledisable100000 level 32 default settings (initial values set by reset command, for all gray scale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ?? 000000 6.24 partial gray scale data registers 1 to 4 (r27 to r30) the partial gray scale data registers specify the gray scale level when using partial four-level gray scale display mode. use of this register optimizes the gray scale display. rx data rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting r27 0, 0 1 ?? pgd5 pgd4 pgd3 pgd2 pgd1 pgd0 ? r28 0, 1 1 ?? pgd5 pgd4 pgd3 pgd2 pgd1 pgd0 ? r29 1, 0 1 ?? pgd5 pgd4 pgd3 pgd2 pgd1 pgd0 ? r30 1, 1 1 ?? pgd5 pgd4 pgd3 pgd2 pgd1 pgd0 ? d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 gray scale level disabledisable000000 level 0 disabledisable000001 level 1 disabledisable000010 level 2 disabledisable000011 level 3 :: disabledisable011111 level 31 disabledisable100000 level 32 default settings (initial values set by reset command, for all partial gray scale data registers) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ?? 000000 data sheet s15745ej2v0ds 66 pD16488A 6.25 power system control register 1 (r32) this command sets the pD16488A's power system mode. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 hpm1 hpm0 ? tcs1 tcs0 op2 op1 op0 flag function hpm1, hpm0 these flags set the driver mode as shown in table 6-9. tcs1, tcs0 these flags set the value for selecting the v reg voltage's temperature curve, as shown in table 6-10. op2 to op0 these flags control the booster's on/off status, the voltage regulator (v regulator) and voltage follower (v/f). the functions controlled via these three bits by the power control setting command are listed in table 6-11. table 6-9. driver mode setting hpm1 hpm0 mode setting 0 0 normal mode 0 1 low-power mode 1 0 high-power mode 1 1 power activation mode table 6-10. selection v reg voltage's temperature curve value tcs1 tcs0 temperature gradient (%/c) v reg (typ.) (v) 00 ? 0.06 1.04 01 ? 0.08 0.98 10 ? 0.09 0.93 11 ? 0.12 0.85 table 6-11. detailed description of functions controlled by flags of power system control 1 status item 10 op2 booster control flag on off op1 v regulator control flag on off op0 voltage follower control flag on off default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00 ? 00111 data sheet s15745ej2v0ds 67 pD16488A 6.26 power system control register 2 (r33) this command is used to control the on-chip register for v lcd voltage regualation. rs e /rd r,/w /wr d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 110 ? vrr2 vrr1 vrr0 ? pvr2 pvr1 pvr0 ? flag function vrr2 to vrr0 when using normal display mode, power system control 2 (v lcd regulator resistance factor setting command) can be used to change the resistance factor at 8 levels. the three flags in power system control 2 set the values shown in table 6-12 as reference values for (1 + rb/ra). pvr2 to pvr0 when using partial display mode, power system control 2 (v lcd regulator resistance factor setting command) can be used to change the resistance factor at 8 levels. the three flags in power system control 2 set the values shown in table 6-12 as reference values for (1 + rb/ra). table 6-12. reference values for v lcd internal resistance factor regulator register register vrr2 vrr1 vrr0 pvr2 pvr1 pvr0 1+rb/ra 000 5 001 8 010 12 011 13 100 16 101 19 110 21 111 24 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ? 000 ? 000 data sheet s15745ej2v0ds 68 pD16488A 6.27 power system control register 3 (r34) this command sets the power system mode, including the bias setting for the pD16488A's normal display mode and the number of boost levels for partial display mode. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 bis2 bis1 bis0 fbs2 fbs1 fbs0 bst1 bst0 ? flag function these three flags select the bias ratio as shown below. bis2 bis1 bis0 bias ratio 0 0 0 1/12 bias 0 0 1 1/11 bias 0 1 0 1/10 bias 0 1 1 1/9 bias 1 0 0 1/8 bias 1 0 1 1/7 bias 1 1 0 prohibited 1 1 1 prohibited bis2 to bis0 note when partial display mode is set, the bias ratio set by the partial mode setting register (r10) is automatically selected. the number of boost levels in booster for normal display mode is selected as shown below. fbs2 fbs1 fbs0 boost level 000x4 001x5 010x6 011x7 100x8 101x9 1 1 0 prohibited fbs2 to fbs0 note 1 1 1 prohibited the number of boost levels in the booster for partial display mode is selected as shown below. bst1 bst0 boost level 00x2 01x3 10x4 bst1, bst0 1 1 prohibited note be sure to execute the halt command before changing these flag settings. default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 data sheet s15745ej2v0ds 69 pD16488A 6.28 electronic volume register (r35) the electronic volume register specifies the electronic volume value for adjusting the contrast when using normal display mode. any value among 256 steps can be selected. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0 ? default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 6.29 partial electronic volume register (r36) the partial electronic volume register specifies the electronic volume value for adjusting the contrast when using partial display mode. any value among 256 steps can be selected. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 pev7 pev6 pev5 pev4 pev3 pev2 pev1 pev0 ? default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 00000000 6.30 boost adjustment register (r37) the voltage (range: 1/8 v dd2 to 7/8 v dd2 ) set to this register is applied to the boost level set for the booster. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 setting 1 ????? ddc2 ddc1 ddc0 ? table 6-13. boost adjustment register (r37) settings ddc2 ddc1 ddc0 boost adjustment voltage 0 0 0 regulator circuit stopped 0 0 1 1/8 v dd2 0 1 0 2/8 v dd2 0 1 1 3/8 v dd2 1 0 0 4/8 v dd2 1 0 1 5/8 v dd2 1 1 0 6/8 v dd2 1 1 1 7/8 v dd2 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ????? 000 data sheet s15745ej2v0ds 70 pD16488A 6.31 ram test mode setting register (r44) the ram test mode setting register directly writes the data for each type of display mode to the display ram, as shown in table 6-15. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ???? rts3 rts2 rts1 rts0 table 6-15. ram test mode setting register (r44) setting rts3 rts2 rts1 rts0 write data 0000normal operation 0100displays list of gray scales 1000all 00/pixel 1001all 11/pixel 1010checker pattern: 00/11 1011checker pattern: 11/00 1100checker pattern: 01/10 1101checker pattern: 10/01 1110vertical striped pattern: 00/11 1111horizontal stri ped pattern: 00/11 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???? 0000 6.32 signature read register (r45) this command is used to read the ic signature set via the sigin1 and sigin2 pins. this is a read-only register. rs d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 ?????? sigin2 sigin1 default settings (initial values set by reset command) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ???????? data sheet s15745ej2v0ds 71 pD16488A 7. list of pD16488A registers 543210 71 1 00 w w ir5ir4ir3ir2ir1ir0 0 1 0 0 0 0 0 0 r/w rmw disp stby bld ivd halt adc comr cres 01000001 r/wfdm dselbwwgraydtyinc 01000010 0 1 0 0 0 0 1 1 r/w xa4 xa3 xa2 xa1 xa0 0 1 0 0 0 1 0 0 r/w ya6 ya5 ya4 ya3 ya2 ya1 ya0 01000101 r/w dt6dt5dt4dt3dt2dt1dt0 0 1 0 0 0 1 1 0 r/w nid6 nid5 nid4 nid3 nid2 nid1 nid0 0 1 0 0 0 1 1 1 w msd6 msd5 msd4 msd3 msd2 msd1 msd0 01001000 w w pid4 pid3 pid2 pid1 pid0 01001001 psd4 psd3 psd2 psd1 psd0 01001010 r/w pbis pdt1pdt0 01001011 r/w 01001100 w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 dsl6 dsl5 dsl4 dsl3 dsl2 dsl1 dsl0 0 1 0 0 1 1 0 1 r/w bxa3 bxa2 bxa1 bxa0 0 1 0 0 1 1 1 0 r/w bsl6 bsl5 bsl4 bsl3 bsl2 bsl1 bsl0 0 1 0 0 1 1 1 1 r/w bel6 bel5 bel4 bel3 bel2 bel1 bel0 01010000 r/w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 r/w 0 1 0 1 0 0 0 1 r/w ixa3 ixa2 ixa1 ixa0 0 1 0 1 0 0 1 0 r/w isl6 isl5 isl4 isl3 isl2 isl1 isl0 0 1 0 1 0 0 1 1 r/w iel6 iel5 iel4 iel3 iel2 iel1 iel0 01010100 0 1 0 1 0 1 0 1 w psl6 psl5 psl4 psl3 psl2 psl1 psl0 01010110 01010111 w gd5gd4gd3gd2gd1gd0 01011000 w gd5gd4gd3gd2gd1gd0 01011001 w gd5gd4gd3gd2gd1gd0 01011010 w gd5gd4gd3gd2gd1gd0 01011011 w pgd5pgd4pgd3pgd2pgd1pgd0 01011100 w pgd5pgd4pgd3pgd2pgd1pgd0 01011101 w pgd5pgd4pgd3pgd2pgd1pgd0 0 1 0 1 1 1 1 0 w pgd5 pgd4 pgd3 pgd2 pgd1 pgd0 01011111 0 1 1 0 0 0 0 0 w hpm1 hpm0 tcs1 tsc0 op2 op1 op0 0 1 1 0 0 0 0 1 w vrr2 vrr1 vrr0 pvr2 pvr1 pvr0 0 1 1 0 0 0 1 0 w bis2 bis1 bis0 fbs2 fbs1 fbs0 bst1 bst0 0 1 1 0 0 0 1 1 w ev7 ev6 ev5 ev4 ev3 ev2 ev1 ev0 0 1 1 0 0 1 0 0 w pev7 pev6 pev5 pev4 pev3 pev2 pev1 pev0 01100101 w ddc2ddc1ddc0 01100110 01100111 01101000 01101001 01101010 01101011 01101100 w r rts3 rts2 rts1 rts0 01101101 sig2 sig1 01101110 01101111 01110000 01110001 01110010 01110011 01110100 01110101 01110110 01110111 01111000 01111001 01111010 01111011 01111100 01111101 01111110 01111111 r/w cs index register register name index register control register 1 x address register y address register duty setting register ac driver inversion cycle register ac driver inversion position shift register partial ac driver inversion cycle register partial ac driver inversion potision shift register partial display mode setting register display memory access register display start line setting register blink x address register inverted x address register inversion start line address register partial start line address register gray scale data register 1 (0, 0) patial gray scale data register 1 (0, 0) power system control register 1 power system control register 2 power system control register 3 electronic volume register partial electronic volume register boost adjustment register ram test mode setting register signature read register patial gray scale data register 2 (0, 1) patial gray scale data register 3 (1, 0) patial gray scale data register 4 (1, 1) gray scale data register 2 (0, 1) gray scale data register 3 (1, 0) gray scale data register 4 (1, 1) inversion end line address register inverted data memory access register blink start line address register blink end line address register blink data memory access register control register 2 reset command data bits rs r1 ir r0 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r59 r60 r61 r62 r63 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 0 6543 2 remark : not to use these registers. data sheet s15745ej2v0ds 72 pD16488A 8. power supply sequence the pD16488A includes power supply circuitry, such as a booster and a voltage follower. w hen a reset is performed using the /res pin, the reset function is restricted so as to prevent operation faults that may occur due to noise effects, etc . when electric charge remains in the smoothing capacitor that is connected between the v ss pin and the voltage pins related to the lcd driver (v lcd , v lc1 to v lc4 ), troubles such as a brief all-black display screen may occur when the power is switched on or off. the following power-on sequence is recommended as a means to avoid such troubles when switching the power on or off. 8.1 power on sequence (when using on-chip power supply, power supply on display on) turn power on when /res pin = l power supply stabilization /res pin = h wait at least 50 s before command input command reset r2 register reset control register 1 disp = 0, halt = 1 r0 display off, internal operations stopped ic functions set via command input ? control register 1 (disp = 0, halt = 1 status is retained) ? control register 2 ? ? ? ? power control register 1 (hpm1, hpm0 = 1, 1) ? power control registers 2, 3 ? electronic volume register ? partial electronic volume register ? boost adjustment register specification of power activation mode user-specified settings via command input duty setting register (r5) ac driver inversion cycle register (r6) function settings for gray scale data, etc. make sure to set the duty setting register (r5) and ac driver inversion cycle register (r6) initialization complete control register 1 disp = 0, halt = 0 r0 display off, internal operations started lcd display screen settings ? display start line setting register ? write screen data, etc. + wait time after internal operations are started, wait at least 400 ms before turning on the lcd display note . power system control register 1 (mode except hpm1, hpm0 (1, 1)) cancels v/f mode for power activation control register 1 disp = 1, halt = 0 r0 display on, internal operation start mode note this 400 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. we recommend determining the wait time after making a thorough evaluation of the actual device (refer to 8.5 v out , v lcd voltage sequence (power on power off) ). ? data sheet s15745ej2v0ds 73 pD16488A 8.2 power off sequence (when using on-chip power supply) operation mode disp = 0, halt = 0 r0 display off , internal operation start mode hpm1 = 1, hpm0 = 0 r32 sets high power mode set electronic volume register r35 [ev7, ev6, ev5, ev4, ev3, ev2, ev1, ev0] = [0, 0, 0, 0, 0, 0, 0, 0] set partial electronic volume register r36 [pev7, pev6, pev5, pev4, pev3, pev2, pev1, pev0] = [0, 0, 0, 0, 0, 0, 0, 0] wait at least 1200 ms before power off note . power supply off note this 1200 ms wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. nec recommends determining the wait time after making a thorough evaluation of the actual device (refer to 8.5 v out , v lcd voltage sequence (power on power off) ). 8.3 power on sequence (when using external driver power supply, power on display on) logic power on when /res pin = l v dd1 , v dd2 power on, v out = hi-z power supply stabilization /res pin = h wait at least 50 s befor command input command reset r2 register reset disp = 0, halt = 1 r0 display off, internal operations stopped initialization via command input (user-specified) selection of ic functions, etc. power system control register 1 (r32) : [op2, op1, op0] = [0 ,0 ,x] disp = 0, halt = 0 r0 display off, internal operations started external lcd driver power supply on v out power supply on stabilization of external lcd driver power supply disp = 1, halt = 0 r0 display on, internal operations started ? data sheet s15745ej2v0ds 74 pD16488A 8.4 power supply off sequence (when using external driver power supply) operation mode disp = 0, halt = 0 r0 display off , internal operation start mode external driver power supply off v out = hi-z disp = 0, halt = 1 r0 display off, internal operations stopped logic power supply off v dd1 , v dd2 , power supply off data sheet s15745ej2v0ds 75 pD16488A 8.5 v out , v lcd voltage sequence (power on power off) v out v dd 0 hpm = 3 select hpm = 0 to 2 select hpm = 0 to 2 partial display v lcd = 15v 6v normal display normal display select hpm = 0 to 2 halt = 0 power on default settings /res pin = 0 /res pin = 1 400 ms disp = 0, halt = 1 disp = 1 disp = 1 disp = 1 disp = 0 hpm = 2 dty = 1 disp = 0 hpm = 3 dty = 0 disp = 0 hpm = 2 ev = 0 power off dotted line: v out solid line: v lcd 1200 ms 400 ms 700 ms conditions: v dd : v dd1 = v dd2 = 3.0 v boost levels: x6 (in normal display mode), x3 (in partial display mode) capacitors: v lcn pin to cn + / ? pin = 1 f, amp out pin, amp outp pin, v rs pin = 0.1 f caution connect a capacitor of less than 0.1 f to both amp out and amp outp pins. data sheet s15745ej2v0ds 76 pD16488A 9. use of ram test mode the pD16488A has a test mode for writing nine types of screen data to display ram. when using the test mode, be sure to execute via the sequence shown below. if executing the test mode by some other sequence, troubles may appear in the screen display. operation mode control register 1 disp = 0, stby = 1 r0 display off , set to standby set ram test mode r44 select ram write data control register 1 disp = 0, stby = 0 r0 display off, cancel standby wait time after internal operations are started, wait at least 1 sec before turning on the lcd display note . control register 1 disp = 1 r0 display on settings complete note this 1 sec wait time varies according to the panel characteristics and the capacitance value of the boost/smoothing capacitor. we recommend determining the wait time after making a thorough evaluation of the actual device. data sheet s15745ej2v0ds 77 pD16488A 10. electrical specifications absolute maximum ratings (t a = +25c, v ss = 0 v) parameter symbol ratings unit logic system supply voltage v dd1 ? 0.3 to + 4.0 v booster supply voltage v dd2 ? 0.3 to + 4.0 v driver supply voltage v out ? 0.3 to + 20.0 v driver reference supply input voltage v lcd , v lc1 to v lc4 ? 0.3 to v out + 0.3 v logic system input voltage v in1 ? 0.3 to v dd1 + 0.3 v logic system output voltage v out1 ? 0.3 to v dd1 + 0.3 v logic system input/output voltage v i/o1 ? 0.3 to v dd1 + 0.3 v driver system input voltage v in2 ? 0.3 to v out + 0.3 v driver system output voltage v out2 ? 0.3 to v out + 0.3 v operating ambient temperature t a ? 40 to + 85 c storage temperature t stg ? 55 to + 125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range parameter symbol min. typ. max. unit logic system supply voltage v dd1 1.7 3.6 v booster supply voltage v dd2 note1 2.4 3.6 v driver system supply voltage v out note2 5.5 18.0 v logic system input voltage v in 0v dd1 v driver system supply voltage v lcd , v lc1 to v lc4 note2 0v out v maximum setting for lcd driver voltage v lcd note3 v out ? 0.5 v notes 1. v dd1 must be less than or equal to v dd2 2. this item is the recommended parameter when the lcd has an external driver. 3. this item is the recommended parameter when an on-chip power supply circuit drives the lcd. cautions 1. when using an external lcd driver, be sure to maintain these relations: v ss < < < < v lc4 < < < < v lc3 < < < < v lc2 < < < < v lc1 < < < < v lcd v out. 2. maintain the relations shown in 8. power supply sequence when turning the power on or off. 3. when using an external resister (when not using an on-chip resister for v lcd adjustment), maintain supply of a voltage between 1.0 v and the v dd1 voltage to the v r and v rs pins. data sheet s15745ej2v0ds 78 pD16488A electrical characteristics 1 (unless otherwise specified, t a = ? 40 to +85 c, v dd1 = 1.7 to 3.6 v, v dd2 = 2.4 to 3.6 v) parameter symbol conditions min. typ. note1 max. unit high-level input voltage v ih 0.8 v dd1 v low-level input voltage v il 0.2 v dd1 v high-level input current i ih1 except for d 7 (si), d 6 (scl) and d 5 to d 0 1 a low-level input current i il1 except for d 7 (si), d 6 (scl) and d 5 to d 0 ? 1 a high-level output voltage v oh i out = ? 1 ma except osc out v dd1 ? 0.5 v low-level output voltage v ol i out = 1 ma except osc out 0.5 v high-level leakage current i loh d 7 (si), d 6 (scl) and d 5 to d 0 ,10 a v in/out = v dd1 low-level leakage current i lol d 7 (si), d 6 (scl) and d 5 to d 0 , ? 10 a v in/out = v ss common output on resistance r com v lcn com n , v out = 15 v, v lcd = 12 v, 4 k ? 1/10 bias, |i o | = 50 a segment output on resistance r seg v lcn seg n , v out = 15 v, v lcd = 12 v, 4 k ? 1/10 bias, |i o | = 50 a driver voltage (boost voltage) v out in x5 boost mode, v dd = 3.0 v, 13.8 v checker pattern display in x6 boost mode, v dd = 3.0 v, 16.6 v checker pattern display reference voltage v reg note2 v dd = 3.0 v, t a = 85 c, tsc1,tsc0 = 1,1 (temperature characteristic curves: ? 0.12%/ c) 0.720 0.790 0.860 v oscillation frequency f osc note3 v dd1 = 3.0 v, t a = 25 c, 1/92 duty, 26.9 khz in b/w mode, r = 1100 k ? v dd1 = 3.0 v, t a = 25 c, 1/38 duty, 10.6 khz in b/w mode, r = 3 m ? notes 1. typ. values are reference values when t a = 25 c (except v reg ). 2. the reference voltage values when t a = 25 c are shown below: min. = 0.775 v, typ.= 0.850 v, max. = 0.925 v 3. the oscillation frequency varies according to the parasitic capacitance of the wiring capacitance. we therefore recommend determining the oscillation resister?s value after making a thorough evaluation of the actual device. ? ? ? data sheet s15745ej2v0ds 79 pD16488A electrical characteristics 2 (unless otherwise specified, t a = ? 40 to +85 c) parameter symbol conditions min. typ. note max. unit current consumption i dd11 frame frequency = 70 hz, 160 220 a (normal mode) b/w all display off data output, 1/92 duty, v dd1 = v dd2 = 3.0 v, in x5 boost mode, v lcd = 12 v frame frequency = 70 hz, 210 310 a b/w checker pattern display data output, 1/92 duty, v dd1 = v dd2 = 3.0 v, in x5 boost mode, v lcd = 12 v current consumption i dd12 frame frequency = 70 hz, 270 390 a (high-power mode) b/w all display off data output, 1/92 duty, v dd1 = v dd2 = 3.0 v, in x5 boost mode, v lcd = 12 v frame frequency = 70 hz, 325 480 a b/w checker pattern display data output, 1/92 duty, v dd1 = v dd2 = 3.0 v, in x5 boost mode, v lcd = 12 v current consumption i dd13 frame frequency = 70 hz, 115 155 a (low-power mode) b/w all display off data output, 1/92 duty, v dd1 = v dd2 = 3.0 v, in x5 boost mode, v lcd = 12 v frame frequency = 70 hz, 165 230 a b/w checker pattern display data output, 1/92 duty, v dd1 = v dd2 = 3.0 v, in x5 boost mode, v lcd = 12 v current consumption i dd21 frame frequency = 70 hz, 95 140 a (partial display mode) b/w all display off data output, 1/38 duty, v dd1 = v dd2 = 3.0 v, in x3 boost mode, v lcd = 7.0 v, normal mode frame frequency = 70 hz, 105 160 a b/w checker pattern display data output, 1/38 duty, v dd1 = v dd2 = 3.0 v, v lcd = 7.0 v, in x3 boost mode, normal mode current consumption i dd22 v dd1 = v dd2 = 3.0 v 10 a (standby mode) note typ. values are reference values when t a = 25 c. data sheet s15745ej2v0ds 80 pD16488A required timing conditions (unless otherwise specified, t a = ? 30 to +85 c) (1) i80 cpu interface t as8 t ah8 t cclw, t cclr t cyc8 t cchr , t cchw t dh8 t ds8 t acc8 t oh8 rs /cs1 (cs2 = h) /wr, /rd d 0 to d 7 (write) d 0 to d 7 (read) t f t r when v dd1 = 1.7 v to 2.0 v parameter symbol conditions min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 1000 ns control low-level pulse width (/wr) t cclw /wr 160 ns control low-level pulse width (/rd) t cclr /rd 430 ns control high-level pulse width (/wr) t cchw /wr 160 ns control high-level pulse width (/rd) t cchr /rd 160 ns data setup time t ds8 d 0 to d 7 160 ns data hold time t dh8 d 0 to d 7 0ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 0 470 ns output disable time t oh8 d 0 to d 7 , c l = 5 pf, r = 3 k ? 0 170 ns note typ. values are reference values when t a = 25 c. data sheet s15745ej2v0ds 81 pD16488A when v dd1 = 2.0 to 2.5 v parameter symbol conditions min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 600 ns control low-level pulse width (/wr) t cclw /wr 120 ns control low-level pulse width (/rd) t cclr /rd 240 ns control high-level pulse width (/wr) t cchw /wr 120 ns control high-level pulse width (/rd) t cchr /rd 120 ns data setup time t ds8 d 0 to d 7 120 ns data hold time t dh8 d 0 to d 7 0ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 0 280 ns output disable time t oh8 d 0 to d 7 , c l = 5 pf, r = 3 k ? 0 170 ns note typ. values are reference values when t a = 25 c. when v dd1 = 2.5 to 3.6 v parameter symbol conditions min. typ. note max. unit address hold time t ah8 rs 0 ns address setup time t as8 rs 0 ns system cycle time t cyc8 250 ns control low-level pulse width (/wr) t cclw /wr 60 ns control low-level pulse width (/rd) t cclr /rd 120 ns control high-level pulse width (/wr) t cchw /wr 60 ns control high-level pulse width (/rd) t cchr /rd 60 ns data setup time t ds8 d 0 to d 7 60 ns data hold time t dh8 d 0 to d 7 0ns /rd access time t acc8 d 0 to d 7 , c l = 100 pf 0 140 ns output disable time t oh8 d 0 to d 5 , c l = 5 pf, r = 3 k ? 070ns note typ. values are reference values when t a = 25 c. /rd /cs1 (cs2 = h) t rd (v dd1 = 1.8 to 3.6 v) parameter symbol conditions min. typ. note max. unit chip select disable time t rd /rd-cs 10 ns note typ. values are reference values when t a = 25 c. cautions 1. the rise and fall times of input signal (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20% or 80% of v dd1 . data sheet s15745ej2v0ds 82 pD16488A (2) m68 cpu interface t as6 t ah6 t ewhr, t ewhw t cyc6 t ewlr, t ewlw t dh6 t ds6 t acc6 t oh6 rs r,/w /cs1 (cs2 = h) e d 0 to d 7 (write) d 0 to d 7 (read) t f t r when v dd1 = 1.7 to 2.0 v parameter symbol conditions min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 1000 ns data setup time t ds6 d 0 to d 7 160 ns data hold time t dh6 d 0 to d 7 0ns access time t acc6 d 0 to d 7 , c l = 100 pf 0 470 ns output disable time t oh6 d 0 to d 7 , c l = 5 pf, r = 3 k ? 0 170 ns enable high pulse width read t ewhr e 430 ns write t ewhw e 160 ns enable low pulse width read t ewlr e 160 ns write t ewlw e 160 ns note typ. values are reference values when t a = 25 c. data sheet s15745ej2v0ds 83 pD16488A when v dd1 = 2.0 to 2.5 v parameter symbol conditions min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 600 ns data setup time t ds6 d 0 to d 7 120 ns data hold time t dh6 d 0 to d 7 0ns access time t acc6 d 0 to d 7 , c l = 100 pf 0 280 ns output disable time t oh6 d 0 to d 7 , c l = 5 pf, r = 3 k ? 0 170 ns enable high pulse width read t ewhr e 240 ns write t ewhw e 120 ns enable low pulse width read t ewlr e 120 ns write t ewlw e 120 ns note typ. values are reference values when t a = 25 c. when v dd1 = 2.5 to 3.6 v parameter symbol conditions min. typ. note max. unit address hold time t ah6 rs 0 ns address setup time t as6 rs 0 ns system cycle time t cyc6 250 ns data setup time t ds6 d 0 to d 7 60 ns data hold time t dh6 d 0 to d 7 0ns access time t acc6 d 0 to d 7 , c l = 100 pf 0 140 ns output disable time t oh6 d 0 to d 7 , c l = 5 pf, r = 3 k ? 070ns enable high pulse width read t ewhr e 120 ns write t ewhw e60 ns enable low pulse width read t ewlr e60 ns write t ewlw e60 ns note typ. values are reference values when t a = 25 c. cautions 1. the rise and fall times of input signals (t r and t f ) are rated at 15 ns or less. when using a fast system cycle time, the rated value range is either (t r + t f ) (t cyc6 ? ? ? ? t ewlw ? ? ? ? t ewhw ) or (t r + t f ) (t cyc6 ? ? ? ? t ewlr ? ? ? ? t ewhr ). 2. all timing is rated based on 20% or 80% of v dd1 . data sheet s15745ej2v0ds 84 pD16488A (3) serial interface t css t f t r t csh t sas t sah t slw t shw t scyc t sds t sdh /cs1 (cs2 = h) rs scl si when v dd1 = 1.7 to 2.5 v parameter symbol conditions min. typ. note max. unit serial clock cycle t scyc scl 250 ns scl high-level pulse width t shw scl 100 ns scl low-level pulse width t slw scl 100 ns address hold time t sah rs 150 ns address setup time t sas rs 150 ns data setup time t sds si 100 ns data hold time t sdh si 100 ns cs - scl time t css cs 150 ns t csh cs 150 ns note typ. values are reference values when t a = 25 c. when v dd1 = 2.5 to 3.6 v parameter symbol conditions min. typ. note max. unit serial clock cycle t scyc scl 150 ns scl high-level pulse width t shw scl 60 ns scl low-level pulse width t slw scl 60 ns address hold time t sah rs 90 ns address setup time t sas rs 90 ns data setup time t sds si 60 ns data hold time t sdh si 60 ns cs - scl time t css cs 90 ns t csh cs 90 ns note typ. values are reference values when t a = 25 c. cautions 1. the rise and fall times of input signal (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20% or 80% of v dd1 . data sheet s15745ej2v0ds 85 pD16488A (4) common parameter symbol conditions min. typ. note max. unit clock input 1 f n when using osc in1 , external clock, and 26.9 150 khz on-chip divider, 1/92 duty, b/w mode when using osc in1 , external clock, and 53.8 150 khz on-chip divider, 1/92 duty, four-level gray scale mode clock input 2 f p when using osc in2 , external clock for 10.6 50 khz partial display mode, but not using on-chip divider, b/w mode when using osc in2 , external clock for 21.3 50 khz partial display mode, but not using on-chip divider, four-level gray scale mode note typ. values are reference values when frame frequency = 70 hz. cautions 1. the rise and fall times of input signal (t r and t f ) are rated as 15 ns or less. 2. all timing is rated based on 20% or 80% of v dd1 . (a) display control output timing fr osc sync t dfr (v dd1 = 1.7 to 2.5 v) parameter symbol conditions min. typ. note max. unit fr delay time t dfr fr, c l = 50 pf 50 200 ns note typ. values are reference values when t a = 25c. (v dd1 = 2.5 to 3.6 v) parameter symbol conditions min. typ. note max. unit fr delay time t dfr fr, c l = 50 pf 20 80 ns note typ. values are reference values when t a = 25c. caution all timing is rated based on 20% or 80% of v dd1 . data sheet s15745ej2v0ds 86 pD16488A (b) reset timing t rw t r /res internal status during reset reset complete when v dd1 = 1.7 to 2.5 v parameter symbol conditions min. typ. note max. unit reset time t r 50 s reset low pulse width t rw /res 50 s note typ. values are reference values when t a = 25 c. when v dd1 = 2.5 to 3.6 v parameter symbol conditions min. typ. note max. unit reset time t r 50 s reset low pulse width t rw /res 50 s note typ. values are reference values when t a = 25 c. caution all timing is rated based on 20% or 80% of v dd1 . data sheet s15745ej2v0ds 87 pD16488A 11. cpu interface (reference example) the pD16488A can be connected to either an i80 series cpu or an m68 series cpu. also, if a serial interface connection is used, the number of signal lines can be reduced. if several pD16488A chip is used, the display area can be enlarged. when using this method, use the chip select signal to select and access the ics. (1) m68 series cpu v cc gnd a0 decoder a1 to a15 vima d 0 to d 7 e r/w /res cpu v dd1 v ss rs /cs1 d 0 to d 7 e r,/w /res /reset psx (2) i80 series cpu v cc gnd a0 decoder a1 to a7 d 0 to d 7 /wr /res /rd /wr /rd /iorq cpu v dd1 v ss rs /cs1 d 0 to d 7 /res /reset psx data sheet s15745ej2v0ds 88 pD16488A (3) when using serial interface v cc gnd a0 decoder a1 to a7 /port2 /res port1 scl(d 6 ) si(d 7 ) open cpu v dd1 v ss rs /cs1 d 0 to d 5 /res /reset psx data sheet s15745ej2v0ds 89 pD16488A [memo] data sheet s15745ej2v0ds 90 pD16488A [memo] data sheet s15745ej2v0ds 91 pD16488A notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. |
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